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* [gcc r12-3508] AVX512FP16: Add testcase for vreduceph/vreducesh/vrndscaleph/vrndscalesh.
@ 2021-09-14 4:35 hongtao Liu
0 siblings, 0 replies; only message in thread
From: hongtao Liu @ 2021-09-14 4:35 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b6e944df4e3b943f084e138042e060a04bb4b24c
commit r12-3508-gb6e944df4e3b943f084e138042e060a04bb4b24c
Author: liuhongt <hongtao.liu@intel.com>
Date: Mon Mar 2 17:05:59 2020 +0800
AVX512FP16: Add testcase for vreduceph/vreducesh/vrndscaleph/vrndscalesh.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx512fp16-helper.h (_ROUND_CUR): New macro.
* gcc.target/i386/avx512fp16-vreduceph-1a.c: New test.
* gcc.target/i386/avx512fp16-vreduceph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vreducesh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vreducesh-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vrndscaleph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vrndscaleph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vrndscalesh-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vrndscalesh-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vreduceph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vreduceph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vrndscaleph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c: Ditto.
Diff:
---
gcc/testsuite/gcc.target/i386/avx512fp16-helper.h | 1 +
.../gcc.target/i386/avx512fp16-vreduceph-1a.c | 26 +++++
.../gcc.target/i386/avx512fp16-vreduceph-1b.c | 116 +++++++++++++++++++++
.../gcc.target/i386/avx512fp16-vreducesh-1a.c | 26 +++++
.../gcc.target/i386/avx512fp16-vreducesh-1b.c | 78 ++++++++++++++
.../gcc.target/i386/avx512fp16-vrndscaleph-1a.c | 26 +++++
.../gcc.target/i386/avx512fp16-vrndscaleph-1b.c | 101 ++++++++++++++++++
.../gcc.target/i386/avx512fp16-vrndscalesh-1a.c | 25 +++++
.../gcc.target/i386/avx512fp16-vrndscalesh-1b.c | 62 +++++++++++
.../gcc.target/i386/avx512fp16vl-vreduceph-1a.c | 30 ++++++
.../gcc.target/i386/avx512fp16vl-vreduceph-1b.c | 16 +++
.../gcc.target/i386/avx512fp16vl-vrndscaleph-1a.c | 30 ++++++
.../gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c | 16 +++
13 files changed, 553 insertions(+)
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h b/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h
index 5d3539bf312..ec88888532c 100644
--- a/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h
@@ -17,6 +17,7 @@
/* Useful macros. */
#define NOINLINE __attribute__((noinline,noclone))
#define _ROUND_NINT (_MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC)
+#define _ROUND_CUR 8
#define AVX512F_MAX_ELEM 512 / 32
/* Structure for _Float16 emulation */
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1a.c
new file mode 100644
index 00000000000..536c1ef6b02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1a.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+#define IMM 123
+
+volatile __m512h x1;
+volatile __mmask32 m;
+
+void extern
+avx512fp16_test (void)
+{
+ x1 = _mm512_reduce_ph (x1, IMM);
+ x1 = _mm512_mask_reduce_ph (x1, m, x1, IMM);
+ x1 = _mm512_maskz_reduce_ph (m, x1, IMM);
+ x1 = _mm512_reduce_round_ph (x1, IMM, 8);
+ x1 = _mm512_mask_reduce_round_ph (x1, m, x1, IMM, 8);
+ x1 = _mm512_maskz_reduce_round_ph (m, x1, IMM, 8);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1b.c
new file mode 100644
index 00000000000..20d1ba59fda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vreduceph-1b.c
@@ -0,0 +1,116 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+#ifndef __REDUCEPH__
+#define __REDUCEPH__
+V512 borrow_reduce_ps(V512 v, int imm8)
+{
+ V512 temp;
+ switch (imm8)
+ {
+ case 1: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 1);break;
+ case 2: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 2);break;
+ case 3: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 3);break;
+ case 4: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 4);break;
+ case 5: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 5);break;
+ case 6: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 6);break;
+ case 7: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 7);break;
+ case 8: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 8);break;
+ }
+ return temp;
+}
+#endif
+
+void NOINLINE
+EMULATE(reduce_ph) (V512 * dest, V512 op1,
+ __mmask32 k, int imm8, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ V512 t1,t2;
+ int i;
+ __mmask16 m1, m2;
+
+ m1 = k & 0xffff;
+ m2 = (k >> 16) & 0xffff;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(*dest, &v7, &v8);
+ t1 = borrow_reduce_ps(v1, imm8);
+ t2 = borrow_reduce_ps(v2, imm8);
+
+ for (i = 0; i < 16; i++) {
+ if (((1 << i) & m1) == 0) {
+ if (zero_mask) {
+ v5.f32[i] = 0;
+ }
+ else {
+ v5.u32[i] = v7.u32[i];
+ }
+ }
+ else {
+ v5.f32[i] = t1.f32[i];
+ }
+
+ if (((1 << i) & m2) == 0) {
+ if (zero_mask) {
+ v6.f32[i] = 0;
+ }
+ else {
+ v6.u32[i] = v8.u32[i];
+ }
+ }
+ else {
+ v6.f32[i] = t2.f32[i];
+ }
+
+ }
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void
+TEST (void)
+{
+ V512 res;
+ V512 exp;
+
+ init_src();
+
+ EMULATE(reduce_ph) (&exp, src1, NET_MASK, 6, 0);
+ HF(res) = INTRINSIC (_reduce_ph) (HF(src1), 6);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _reduce_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(reduce_ph) (&exp, src1, MASK_VALUE, 5, 0);
+ HF(res) = INTRINSIC (_mask_reduce_ph) (HF(res), MASK_VALUE, HF(src1), 5);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_reduce_ph);
+
+ EMULATE(reduce_ph) (&exp, src1, ZMASK_VALUE, 4, 1);
+ HF(res) = INTRINSIC (_maskz_reduce_ph) (ZMASK_VALUE, HF(src1), 4);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_reduce_ph);
+
+#if AVX512F_LEN == 512
+ EMULATE(reduce_ph) (&exp, src1, NET_MASK, 6, 0);
+ HF(res) = INTRINSIC (_reduce_round_ph) (HF(src1), 6, _ROUND_CUR);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _reduce_round_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(reduce_ph) (&exp, src1, MASK_VALUE, 5, 0);
+ HF(res) = INTRINSIC (_mask_reduce_round_ph) (HF(res), MASK_VALUE, HF(src1), 5, _ROUND_CUR);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_reduce_round_ph);
+
+ EMULATE(reduce_ph) (&exp, src1, ZMASK_VALUE, 4, 1);
+ HF(res) = INTRINSIC (_maskz_reduce_round_ph) (ZMASK_VALUE, HF(src1), 4, _ROUND_CUR);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_reduce_round_ph);
+#endif
+
+ if (n_errs != 0) {
+ abort ();
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1a.c
new file mode 100644
index 00000000000..80369918567
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1a.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vreducesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vreducesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreducesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreducesh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreducesh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+
+#include <immintrin.h>
+
+#define IMM 123
+
+volatile __m128h x1, x2;
+volatile __mmask8 m;
+
+void extern
+avx512fp16_test (void)
+{
+ x1 = _mm_reduce_sh (x1, x2, IMM);
+ x1 = _mm_mask_reduce_sh(x1, m, x1, x2, IMM);
+ x1 = _mm_maskz_reduce_sh(m, x1, x2, IMM);
+ x1 = _mm_reduce_round_sh (x1, x2, IMM, 4);
+ x1 = _mm_mask_reduce_round_sh(x1, m, x1, x2, IMM, 8);
+ x1 = _mm_maskz_reduce_round_sh(m, x1, x2, IMM, 8);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1b.c
new file mode 100644
index 00000000000..4c5dfe73c3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vreducesh-1b.c
@@ -0,0 +1,78 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS 8
+
+V512 borrow_reduce_ps(V512 v, int imm8)
+{
+ V512 temp;
+ switch (imm8)
+ {
+ case 1: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 1);break;
+ case 2: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 2);break;
+ case 3: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 3);break;
+ case 4: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 4);break;
+ case 5: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 5);break;
+ case 6: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 6);break;
+ case 7: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 7);break;
+ case 8: temp.zmm = _mm512_mask_reduce_ps (v.zmm, 0xffff, v.zmm, 8);break;
+ }
+ return temp;
+}
+
+void NOINLINE
+emulate_reduce_sh(V512 * dest, V512 op1,
+ __mmask32 k, int imm8, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ V512 t1;
+ int i;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(*dest, &v7, &v8);
+ t1 = borrow_reduce_ps(v1, imm8);
+
+ if ((k&1) || !k)
+ v5.f32[0] = t1.f32[0];
+ else if (zero_mask)
+ v5.f32[0] = 0;
+ else
+ v5.f32[0] = v7.f32[0];
+
+ for (i = 1; i < 8; i++)
+ v5.f32[i] = v1.f32[i];
+
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void
+test_512 (void)
+{
+ V512 res;
+ V512 exp;
+
+ init_src();
+
+ emulate_reduce_sh(&exp, src1, 0x1, 8, 0);
+ res.xmmh[0] = _mm_reduce_round_sh(src1.xmmh[0], exp.xmmh[0], 8, _ROUND_CUR);
+ check_results(&res, &exp, N_ELEMS, "_mm_reduce_round_sh");
+
+ init_dest(&res, &exp);
+ emulate_reduce_sh(&exp, src1, 0x1, 7, 0);
+ res.xmmh[0] = _mm_mask_reduce_round_sh(res.xmmh[0], 0x1, src1.xmmh[0], exp.xmmh[0], 7, _ROUND_CUR);
+ check_results(&res, &exp, N_ELEMS, "_mm_mask_reduce_round_sh");
+
+ emulate_reduce_sh(&exp, src1, 0x3, 6, 1);
+ res.xmmh[0] = _mm_maskz_reduce_round_sh(0x3, src1.xmmh[0], exp.xmmh[0], 6, _ROUND_CUR);
+ check_results(&res, &exp, N_ELEMS, "_mm_maskz_reduce_round_sh");
+
+
+ if (n_errs != 0) {
+ abort ();
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1a.c
new file mode 100644
index 00000000000..8a307274a9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1a.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+#define IMM 123
+
+volatile __m512h x1;
+volatile __mmask32 m;
+
+void extern
+avx512fp16_test (void)
+{
+ x1 = _mm512_roundscale_ph (x1, IMM);
+ x1 = _mm512_mask_roundscale_ph (x1, m, x1, IMM);
+ x1 = _mm512_maskz_roundscale_ph (m, x1, IMM);
+ x1 = _mm512_roundscale_round_ph (x1, IMM, 8);
+ x1 = _mm512_mask_roundscale_round_ph (x1, m, x1, IMM, 8);
+ x1 = _mm512_maskz_roundscale_round_ph (m, x1, IMM, 8);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1b.c
new file mode 100644
index 00000000000..d50e75585f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscaleph-1b.c
@@ -0,0 +1,101 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+void NOINLINE
+EMULATE(roundscale_ph) (V512 * dest, V512 op1,
+ __mmask32 k, int zero_mask, int round)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ int i;
+ __mmask16 m1, m2;
+ V512 t1, t2;
+ m1 = k & 0xffff;
+ m2 = (k >> 16) & 0xffff;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(*dest, &v7, &v8);
+ if (round==0)
+ {
+ t1.zmm = _mm512_maskz_roundscale_ps (0xffff, v1.zmm, 0x11);
+ t2.zmm = _mm512_maskz_roundscale_ps (0xffff, v2.zmm, 0x11);
+ }
+ else
+ {
+ t1.zmm = _mm512_maskz_roundscale_ps (0xffff, v1.zmm, 0x14);
+ t2.zmm = _mm512_maskz_roundscale_ps (0xffff, v2.zmm, 0x14);
+ }
+ for (i = 0; i < 16; i++)
+ {
+ if (((1 << i) & m1) == 0) {
+ if (zero_mask) {
+ v5.f32[i] = 0;
+ }
+ else {
+ v5.u32[i] = v7.u32[i];
+ }
+ }
+ else {
+ v5.f32[i] = t1.f32[i];
+ }
+
+ if (((1 << i) & m2) == 0) {
+ if (zero_mask) {
+ v6.f32[i] = 0;
+ }
+ else {
+ v6.u32[i] = v8.u32[i];
+ }
+ }
+ else {
+ v6.f32[i] = t2.f32[i];
+ }
+ }
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void
+TEST (void)
+{
+ V512 res, exp;
+
+ init_src();
+
+ EMULATE(roundscale_ph) (&exp, src1, NET_MASK, 0, 1);
+ HF(res) = INTRINSIC (_roundscale_ph) (HF(src1), 0x13);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _roundscale_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(roundscale_ph) (&exp, src1, MASK_VALUE, 0, 1);
+ HF(res) = INTRINSIC (_mask_roundscale_ph) (HF(res), MASK_VALUE, HF(src1), 0x14);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_roundscale_ph);
+
+ EMULATE(roundscale_ph) (&exp, src1, ZMASK_VALUE, 1, 1);
+ HF(res) = INTRINSIC (_maskz_roundscale_ph) (ZMASK_VALUE, HF(src1), 0x14);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_roundscale_ph);
+
+#if AVX512F_LEN == 512
+ EMULATE(roundscale_ph) (&exp, src1, NET_MASK, 0, 1);
+ HF(res) = INTRINSIC (_roundscale_round_ph) (HF(src1), 0x13, 0x08);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _roundscale_round_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(roundscale_ph) (&exp, src1, MASK_VALUE, 0, 1);
+ HF(res) = INTRINSIC (_mask_roundscale_round_ph) (HF(res), MASK_VALUE, HF(src1), 0x14, 0x08);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_roundscale_round_ph);
+
+ EMULATE(roundscale_ph) (&exp, src1, ZMASK_VALUE, 1, 1);
+ HF(res) = INTRINSIC (_maskz_roundscale_round_ph) (ZMASK_VALUE, HF(src1), 0x14, 0x08);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_roundscale_round_ph);
+#endif
+
+ if (n_errs != 0) {
+ abort ();
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1a.c
new file mode 100644
index 00000000000..bd41b634aff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1a.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vrndscalesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vrndscalesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscalesh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscalesh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscalesh\[ \\t\]+\[^\n\]*\{sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+#define IMM 123
+
+volatile __m128h x1, x2;
+volatile __mmask8 m;
+
+void extern
+avx512fp16_test (void)
+{
+ x1 = _mm_roundscale_sh (x1, x2, IMM);
+ x1 = _mm_mask_roundscale_sh(x1, m, x1, x2, IMM);
+ x1 = _mm_maskz_roundscale_sh(m, x1, x2, IMM);
+ x1 = _mm_roundscale_round_sh (x1, x2, IMM, 4);
+ x1 = _mm_mask_roundscale_round_sh(x1, m, x1, x2, IMM, 8);
+ x1 = _mm_maskz_roundscale_round_sh(m, x1, x2, IMM, 8);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1b.c
new file mode 100644
index 00000000000..c1033892878
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrndscalesh-1b.c
@@ -0,0 +1,62 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS 8
+
+void NOINLINE
+emulate_roundscale_sh(V512 * dest, V512 op1,
+ __mmask8 k, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ V512 t1,t2;
+ int i;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(*dest, &v7, &v8);
+ t1.zmm = _mm512_maskz_roundscale_ps (0xffff, v1.zmm, 0x14);
+ t2.zmm = _mm512_maskz_roundscale_ps (0xffff, v2.zmm, 0x14);
+
+ if ((k&1) || !k)
+ v5.f32[0] = t1.f32[0];
+ else if (zero_mask)
+ v5.f32[0] = 0;
+ else
+ v5.f32[0] = v7.f32[0];
+
+ for (i = 1; i < 8; i++)
+ v5.f32[i] = v1.f32[i];
+
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void
+test_512 (void)
+{
+ V512 res;
+ V512 exp;
+
+ init_src();
+
+ emulate_roundscale_sh(&exp, src1, 0x1, 0);
+ res.xmmh[0] = _mm_roundscale_round_sh(src1.xmmh[0], src1.xmmh[0], 0x1, 0x08);
+ check_results(&res, &exp, N_ELEMS, "_mm_roundscale_round_sh");
+
+ init_dest(&res, &exp);
+ emulate_roundscale_sh(&exp, src1, 0x1, 0);
+ res.xmmh[0] = _mm_mask_roundscale_round_sh(res.xmmh[0],
+ 0x1, src1.xmmh[0], src1.xmmh[0], 0x1, 0x08);
+ check_results(&res, &exp, N_ELEMS, "_mm_mask_roundscale_round_sh");
+
+ emulate_roundscale_sh(&exp, src1, 0x3, 1);
+ res.xmmh[0] = _mm_maskz_roundscale_round_sh(0x3, src1.xmmh[0], src1.xmmh[0], 0x1, 0x08);
+ check_results(&res, &exp, N_ELEMS, "_mm_maskz_roundscale_round_sh");
+
+
+ if (n_errs != 0)
+ abort ();
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1a.c
new file mode 100644
index 00000000000..4f43abd5411
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1a.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vreduceph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+#define IMM 123
+
+volatile __m256h x2;
+volatile __m128h x3;
+volatile __mmask8 m8;
+volatile __mmask16 m16;
+
+void extern
+avx512fp16_test (void)
+{
+ x2 = _mm256_reduce_ph (x2, IMM);
+ x3 = _mm_reduce_ph (x3, IMM);
+
+ x2 = _mm256_mask_reduce_ph (x2, m16, x2, IMM);
+ x3 = _mm_mask_reduce_ph (x3, m8, x3, IMM);
+
+ x2 = _mm256_maskz_reduce_ph (m8, x2, IMM);
+ x3 = _mm_maskz_reduce_ph (m16, x3, IMM);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1b.c
new file mode 100644
index 00000000000..38515976ce6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vreduceph-1b.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define DEBUG
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vreduceph-1b.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vreduceph-1b.c"
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1a.c
new file mode 100644
index 00000000000..9fcf7e9b7bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1a.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscaleph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+#define IMM 123
+
+volatile __m256h x2;
+volatile __m128h x3;
+volatile __mmask8 m8;
+volatile __mmask16 m16;
+
+void extern
+avx512fp16_test (void)
+{
+ x2 = _mm256_roundscale_ph (x2, IMM);
+ x3 = _mm_roundscale_ph (x3, IMM);
+
+ x2 = _mm256_mask_roundscale_ph (x2, m16, x2, IMM);
+ x3 = _mm_mask_roundscale_ph (x3, m8, x3, IMM);
+
+ x2 = _mm256_maskz_roundscale_ph (m8, x2, IMM);
+ x3 = _mm_maskz_roundscale_ph (m16, x3, IMM);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c
new file mode 100644
index 00000000000..04b00e2db2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrndscaleph-1b.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define DEBUG
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vrndscaleph-1b.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vrndscaleph-1b.c"
+
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2021-09-14 4:35 [gcc r12-3508] AVX512FP16: Add testcase for vreduceph/vreducesh/vrndscaleph/vrndscalesh hongtao Liu
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