[gcc(refs/users/meissner/heads/work068)] Fixup XXSPLTIDP code generation.

[gcc(refs/users/meissner/heads/work068)] Fixup XXSPLTIDP code generation.

[Michael Meissner]

https://gcc.gnu.org/g:6bdfefa14685345188b31e3775018f750517d587

commit 6bdfefa14685345188b31e3775018f750517d587
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Sep 15 16:17:19 2021 -0400

    Fixup XXSPLTIDP code generation.
    
    2021-09-15  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/predicates.md (easy_fp_constant_sfmode):  Fix
            endian issue for integer values.  Add comment about IEEE 32-bit
            format.
            * config/rs6000/rs6000.c (xxspltidp_constant_immediate): Fix
            endian issue for integer values.
            * config/rs6000/rs6000.md (movdi_internal64): Use ^wa instead of
            $wa for XXSPLTIDP constants.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-splat-constant-di.c: New file.
            * gcc.target/powerpc/vec-splat-constant-v2di.c: New file.

Diff:
---
 gcc/config/rs6000/predicates.md                    |  7 ++-
 gcc/config/rs6000/rs6000.c                         |  4 +-
 gcc/config/rs6000/rs6000.md                        |  2 +-
 .../gcc.target/powerpc/vec-splat-constant-di.c     | 70 ++++++++++++++++++++++
 .../gcc.target/powerpc/vec-splat-constant-v2di.c   | 50 ++++++++++++++++
 5 files changed, 128 insertions(+), 5 deletions(-)

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 105629c0344..d3e04e595dd 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -684,8 +684,8 @@
       df_words[0] = (df_value >> 32) & 0xffffffff;
       df_words[1] = df_value & 0xffffffff;
 
-      /* real_from_target takes the target words in little endian order.  */
-      if (BYTES_BIG_ENDIAN)
+      /* real_from_target takes the target words in  target order.  */
+      if (!BYTES_BIG_ENDIAN)
 	std::swap (df_words[0], df_words[1]);
 
       real_from_target (&rv_type, df_words, DFmode);
@@ -709,6 +709,9 @@
   long sf_value;
   real_to_target (&sf_value, rv, SFmode);
 
+  /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
+     and 23 bits for the mantissa.  Subnormal numbers have the exponent all
+     0 bits, and the mantissa non-zero.  */
   if (((sf_value & 0x7F800000) == 0) && ((sf_value & 0x7FFFFF) != 0))
     return false;
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index a325e753a14..b0a7f20ad83 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6622,8 +6622,8 @@ xxspltidp_constant_immediate (rtx op, machine_mode mode)
       df_words[0] = (df_value >> 32) & 0xffffffff;
       df_words[1] = df_value & 0xffffffff;
 
-      /* real_to_target takes input in little-endian fasion.  */
-      if (BYTES_BIG_ENDIAN)
+      /* real_to_target takes input in target endian order.  */
+      if (!BYTES_BIG_ENDIAN)
 	std::swap (df_words[0], df_words[1]);
 
       REAL_VALUE_TYPE r;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ac7ff217e00..bc7fd3a9d02 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -9333,7 +9333,7 @@
 (define_insn "*movdi_internal64"
   [(set (match_operand:DI 0 "nonimmediate_operand"
 	  "=YZ,        r,          r,
-	   $wa,
+	   ^wa,
 	   r,          r,          r,          r,
 	   m,          ^d,         ^d,
 	   wY,         Z,          $v,         $v,         ^wa,
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
new file mode 100644
index 00000000000..dd896e5385d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
@@ -0,0 +1,70 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+
+/* Test generating DImode constants that have the same bit pattern as DFmode
+   constants that can be loaded with the XXSPLTIDP instruction with the ISA 3.1
+   (power10).  We use asm to force the value into vector registers.  */
+
+double
+scalar_0 (void)
+{
+  /* XXSPLTIB or XXLXOR.  */
+  double d;
+  long long ll = 0;
+
+  __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
+  return d;
+}
+
+double
+scalar_1 (void)
+{
+  /* VSPLTISW/VUPKLSW or XXSPLTIB/VEXTSB2D.  */
+  double d;
+  long long ll = 1;
+
+  __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
+  return d;
+}
+
+/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
+   with XXSPLTIDP.  */
+double
+scalar_float_neg_0 (void)
+{
+  /* XXSPLTIDP.  */
+  double d;
+  long long ll = 0x8000000000000000LL;
+
+  __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
+  return d;
+}
+
+/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
+   XXSPLTIDP.  */
+double
+scalar_float_1_0 (void)
+{
+  /* XXSPLTIDP.  */
+  double d;
+  long long ll = 0x3ff0000000000000LL;
+
+  __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
+  return d;
+}
+
+/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
+   with XXSPLTIDP.  */
+double
+scalar_pi (void)
+{
+  /* PLXV.  */
+  double d;
+  long long ll = 0x400921fb54442d18LL;
+
+  __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
+  return d;
+}
+
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
new file mode 100644
index 00000000000..4d44f943d26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+
+/* Test generating V2DImode constants that have the same bit pattern as
+   V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
+   the ISA 3.1 (power10).  */
+
+vector long long
+vector_0 (void)
+{
+  /* XXSPLTIB or XXLXOR.  */
+  return (vector long long) { 0LL, 0LL };
+}
+
+vector long long
+vector_1 (void)
+{
+  /* XXSPLTIB and VEXTSB2D.  */
+  return (vector long long) { 1LL, 1LL };
+}
+
+/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
+   with XXSPLTISDP.  */
+vector long long
+vector_float_neg_0 (void)
+{
+  /* XXSPLTIDP.  */
+  return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
+}
+
+/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
+   XXSPLTISDP.  */
+vector long long
+vector_float_1_0 (void)
+{
+  /* XXSPLTIDP.  */
+  return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
+}
+
+/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
+   with XXSPLTIDP.  */
+vector long long
+scalar_pi (void)
+{
+  /* PLXV.  */
+  return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
+}
+
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */