[gcc(refs/vendors/ARM/heads/morello)] morello: Implement purecap TLS scheme

[gcc(refs/vendors/ARM/heads/morello)] morello: Implement purecap TLS scheme

[Matthew Malcomson]

https://gcc.gnu.org/g:24def1312970e57d55d44d1b72d7cba2bb285053

commit 24def1312970e57d55d44d1b72d7cba2bb285053
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Thu Sep 9 11:52:46 2021 +0100

    morello: Implement purecap TLS scheme
    
    This patch implements the purecap TLS ABI described here:
    https://github.com/ARM-software/abi-aa/pull/80
    
    gcc/ChangeLog:
    
      * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Use
      new purecap TLS scheme.
      (aarch64_classify_tls_symbol): Force Global Dynamic model for purecap.
      * config/aarch64/aarch64.md (@aarch64_load_tp_hard_<mode>): Use
      correct system register for Morello.
      (tlsdesc_purecap): New.
      (tlsdesc_small_advsimd_<mode>): Disable for purecap.

Diff:
---
 gcc/config/aarch64/aarch64.c  | 16 +++++++++++++---
 gcc/config/aarch64/aarch64.md | 32 ++++++++++++++++++++++++++++++--
 2 files changed, 43 insertions(+), 5 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 2ec8ce6968c..e924a94f048 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3277,14 +3277,20 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
 	gcc_assert (mode == Pmode || mode == ptr_mode);
 	const auto sa = as_a <scalar_addr_mode> (mode);
 
-	rtx x0 = gen_rtx_REG (offset_mode (sa), R0_REGNUM);
-	rtx tp;
+	if (TARGET_CAPABILITY_PURE)
+	  {
+	    aarch64_load_tp (gen_rtx_REG (Pmode, R2_REGNUM));
+	    check_emit_insn (gen_tlsdesc_purecap (imm));
+	    emit_move_insn (dest, gen_rtx_REG (CADImode, R0_REGNUM));
+	    return;
+	  }
 
 	/* In ILP32, the got entry is always of SImode size.  Unlike
 	   small GOT, the dest is fixed at reg 0.  */
 	check_emit_insn (gen_tlsdesc_small (ptr_mode, imm));
 
-	tp = aarch64_load_tp (NULL);
+	rtx x0 = gen_rtx_REG (offset_mode (sa), R0_REGNUM);
+	rtx tp = aarch64_load_tp (NULL);
 
 	if (mode != Pmode)
 	  tp = gen_lowpart (mode, tp);
@@ -16326,6 +16332,10 @@ aarch64_classify_tls_symbol (rtx x)
 {
   enum tls_model tls_kind = tls_symbolic_operand_type (x);
 
+  /* For purecap Morello, we have to use the global dynamic model.  */
+  if (TARGET_CAPABILITY_PURE)
+    return SYMBOL_SMALL_TLSDESC;
+
   switch (tls_kind)
     {
     case TLS_MODEL_GLOBAL_DYNAMIC:
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d885eb8de3e..936079b1fb6 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -6889,7 +6889,12 @@
   [(set (match_operand:ADDR 0 "register_operand" "=r")
 	(unspec:ADDR [(const_int 0)] UNSPEC_TLS))]
   ""
-  "mrs\\t%0, tpidr_el0"
+  {
+    if (TARGET_MORELLO && <MODE>mode == CADImode)
+      return "mrs\\t%0, ctpidr_el0";
+    else
+      return "mrs\\t%0, tpidr_el0";
+  }
   [(set_attr "type" "mrs")]
 )
 
@@ -7025,6 +7030,29 @@
   }
 )
 
+(define_insn "tlsdesc_purecap"
+  [(set (reg:CADI R0_REGNUM)
+	(unspec:CADI [(match_operand 0 "aarch64_valid_symref" "S")]
+		     UNSPEC_TLSDESC))
+   (clobber (reg:CADI LR_REGNUM))
+   (clobber (reg:CC CC_REGNUM))
+   (clobber (reg:CADI R1_REGNUM))
+   (use (reg:CADI FP_REGNUM))
+   (use (reg:CADI R2_REGNUM))]
+  "TARGET_CAPABILITY_PURE"
+  {
+    return "nop\;"
+	   "adrp\\tc0, %A0\;"
+	   "ldr\\tc1, [c0, #%L0]\;"
+	   "add\\tc0, c0, %L0\;"
+	   ".tlsdesccall\\t%0\;"
+	   "blr\\tc1\;"
+	   "scbnds\tc0, c0, x1";
+  }
+  [(set_attr "type" "call")
+   (set_attr "length" "24")])
+
+
 ;; tlsdesc calls preserve all core and Advanced SIMD registers except
 ;; R0 and LR.
 (define_insn "tlsdesc_small_advsimd_<mode>"
@@ -7035,7 +7063,7 @@
    (clobber (reg:CC CC_REGNUM))
    (clobber (match_scratch:<P_OF_PTR> 1 "=r"))
    (use (reg:<P_OF_PTR> FP_REGNUM))]
-  "TARGET_TLS_DESC && !TARGET_SVE"
+  "TARGET_TLS_DESC && !TARGET_CAPABILITY_PURE && !TARGET_SVE"
   {
     if (<MODE>mode == CADImode)
       return "adrp\\tx0, %A0\;ldr\\t%<w>1, [x0, #%L0]\;add\\tx0, x0, %L0\;.tlsdesccall\\t%0\;blr\\t%1";