[gcc(refs/vendors/ARM/heads/morello)] aarch64: Correct feature bits for Morello

[gcc(refs/vendors/ARM/heads/morello)] aarch64: Correct feature bits for Morello

[Matthew Malcomson]

https://gcc.gnu.org/g:e9fbbdad81a49bfc7a00f49cc15879099a658a4b

commit e9fbbdad81a49bfc7a00f49cc15879099a658a4b
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Mon Sep 13 09:22:39 2021 +0100

    aarch64: Correct feature bits for Morello
    
    As it stands, GCC's architecture feature bits for Morello include
    FP16FML (i.e. Armv8.2-FHM) but not FP16: this is an invalid
    combination, and was leading to ICEs in the tests for the FP16FML
    intrinsics. Looking at the Morello Arm ARM [1], it seems Morello wants
    the feature FP16 (Armv8.2-FP16) but not FP16FML.
    
    [1] : https://developer.arm.com/documentation/ddi0606/latest
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64.h (AARCH64_FL_FOR_MORELLO): Switch
            AARCH64_FL_F16FML for AARCH64_FL_F16.
            * config/aarch64/arm_neon.h: Enable fp16fml explicitly for
            Morello.

Diff:
---
 gcc/config/aarch64/aarch64.h  | 2 +-
 gcc/config/aarch64/arm_neon.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 690745bc737..8a87719f52f 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -268,7 +268,7 @@ extern unsigned aarch64_architecture_version;
   (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_V8_6 | AARCH64_FL_FPSIMD \
    | AARCH64_FL_I8MM | AARCH64_FL_BF16)
 #define AARCH64_FL_FOR_MORELLO			\
-  (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16FML | AARCH64_FL_DOTPROD \
+  (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_DOTPROD \
    | AARCH64_FL_RCPC | AARCH64_FL_SSBS | AARCH64_FL_A64C)
 
 /* Macros to test ISA flags.  */
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 412befdb8c1..45e86a844bd 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -34196,7 +34196,7 @@ vcmlaq_rot270_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b,
 #pragma GCC push_options
 
 #ifdef __ARM_FEATURE_C64
-#pragma GCC target ("arch=morello+c64")
+#pragma GCC target ("arch=morello+c64+fp16fml")
 #else
 #pragma GCC target ("arch=armv8.2-a+fp16fml")
 #endif