[gcc(refs/users/meissner/heads/work070)] Update insn count for XXSPLTIDP.

[gcc(refs/users/meissner/heads/work070)] Update insn count for XXSPLTIDP.

[Michael Meissner]

https://gcc.gnu.org/g:0192f1170c76dc6015d7a557f05ee5d1443484f5

commit 0192f1170c76dc6015d7a557f05ee5d1443484f5
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Oct 5 14:22:57 2021 -0400

    Update insn count for XXSPLTIDP.
    
    This patch updates the insn count once the XXSPLTIDP instruction is generated.
    
    2021-10-05  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/testsuite/
    
            * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
            regex for power10.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index bd1502bb30a..dcb30e1d886 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,11 +24,12 @@ vector signed long long splats4(void)
         return (vector signed long long) vec_sl(mzero, mzero);
 }
 
-/* Codegen will consist of splat and shift instructions for most types.
-   If folding is enabled, the vec_sl tests using vector long long type will
-   generate a lvx instead of a vspltisw+vsld pair.  */
+/* Codegen will consist of splat and shift instructions for most types.  If
+   folding is enabled, the vec_sl tests using vector long long type will
+   generate a lvx instead of a vspltisw+vsld pair.  On power10, it will
+   generate a xxspltidp instruction instead of the lvx.  */
 
 /* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
 /* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */