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* [gcc(refs/users/meissner/heads/work070)] Revert patch.
@ 2021-10-05 21:12 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-10-05 21:12 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:814e599452a2e836d247db1c3d2646d672ab2bb3
commit 814e599452a2e836d247db1c3d2646d672ab2bb3
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Oct 5 17:12:26 2021 -0400
Revert patch.
2021-10-04 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/float128-constant.c: New test.
Diff:
---
.../gcc.target/powerpc/float128-constant.c | 144 ---------------------
1 file changed, 144 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index 23ee7e85d84..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 18 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work070)] Revert patch.
@ 2021-10-05 21:08 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-10-05 21:08 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2d40780b819ada050aac8d26f566c265f0e3fd9a
commit 2d40780b819ada050aac8d26f566c265f0e3fd9a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Oct 5 17:07:25 2021 -0400
Revert patch.
2021-10-04 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-di.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
Diff:
---
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 -------------------
.../gcc.target/powerpc/vec-splat-constant-di.c | 70 ----------------------
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 -------------------
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 --------------------
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 ----------------
5 files changed, 304 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
deleted file mode 100644
index 75714d0b11d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating DImode constants that have the same bit pattern as DFmode
- constants that can be loaded with the XXSPLTIDP instruction with the ISA 3.1
- (power10). We use asm to force the value into vector registers. */
-
-double
-scalar_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- double d;
- long long ll = 0;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-double
-scalar_1 (void)
-{
- /* VSPLTISW/VUPKLSW or XXSPLTIB/VEXTSB2D. */
- double d;
- long long ll = 1;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTIDP. */
-double
-scalar_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x8000000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTIDP. */
-double
-scalar_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x3ff0000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-double
-scalar_pi (void)
-{
- /* PLXV. */
- double d;
- long long ll = 0x400921fb54442d18LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work070)] Revert patch.
@ 2021-10-04 21:49 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-10-04 21:49 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:84e89b77768ad97c1fc3a74ad37174854dc10c3f
commit 84e89b77768ad97c1fc3a74ad37174854dc10c3f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Oct 4 17:48:24 2021 -0400
Revert patch.
2021-10-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can use
LXVKQ, it is an easy floating point constant.
(easy_fp_constant_ieee128): New predicate.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_immediate):
New declaration.
* config/rs6000/rs6000.c (xxspltidp_constant_immediate): New
function.
(output_vec_const_move): Add support for LXVKQ.
(rs6000_output_move_128bit): Likewise.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/float128-constant.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 5 -
gcc/config/rs6000/predicates.md | 78 -----------
gcc/config/rs6000/rs6000-protos.h | 1 -
gcc/config/rs6000/rs6000.c | 102 ---------------
gcc/config/rs6000/rs6000.opt | 4 -
gcc/config/rs6000/vsx.md | 28 ++--
gcc/doc/md.texi | 3 -
.../gcc.target/powerpc/float128-constant.c | 144 ---------------------
8 files changed, 14 insertions(+), 351 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 1700657abe9..1ff46c9f4fc 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -223,11 +223,6 @@
"A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction."
(match_operand 0 "easy_vector_constant_64bit_element"))
-;; KF/TF scalar than can be loaded with LXVKQ
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "easy_fp_constant_ieee128"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 30e89ec79f0..7544ac87700 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -606,11 +606,6 @@
if (easy_fp_constant_64bit_scalar (op, mode))
return 1;
- /* If we have the ISA 3.1 LXVKQ instruction, see if the constant can be loaded
- with that instruction. */
- if (easy_fp_constant_ieee128 (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -782,79 +777,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is an IEEE 128-bit special constant that can be
-;; loaded with the LXVKQ instruction.
-(define_predicate "easy_fp_constant_ieee128"
- (match_code "const_double")
-{
- if (!TARGET_LXVKQ || !TARGET_POWER10 || !TARGET_VSX || !TARGET_FLOAT128_HW)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (!FLOAT128_IEEE_P (mode))
- return false;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- /* Special values (+/-infinity, -0.0. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- if (real_isinf (rv) || real_isnegzero (rv))
- return true;
-
- /* Only recognize the normal NaN. Do not recognize NaNs with the negative
- sign, signaling NaNs, or NaNs that have non-zero mantissa. */
- if (real_isnan (rv))
- {
- long w[4];
-
- real_to_target (&w[0], rv, mode);
- return (BYTES_BIG_ENDIAN
- ? (w[0] == 0x7fff8000 && w[1] == 0 && w[2] == 0 && w[3] == 0)
- : (w[3] == 0x7fff8000 && w[2] == 0 && w[1] == 0 && w[0] == 0));
- }
-
- if (real_issignaling_nan (rv))
- return false;
-
- /* All of the values generated can be expressed as SFmode values, if it
- doesn't fit in SFmode, exit. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* The other values are all integers 1..7, and -1..-7. */
- if (!real_isinteger (rv, mode))
- return false;
-
- HOST_WIDE_INT value = real_to_integer (rv);
- switch (value)
- {
- default:
- break;
-
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case -1:
- case -2:
- case -3:
- case -4:
- case -5:
- case -6:
- case -7:
- return true;
- }
-
- /* We can't load the value with LXVKQ. */
- return false;
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index a21fa08b367..e9be9c4d99f 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -33,7 +33,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern int easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
extern long xxspltidp_constant_immediate (rtx, machine_mode);
-extern int lxvkq_constant_immediate (rtx, machine_mode);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7b0b5357f0b..83d243269e3 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -7000,96 +7000,6 @@ xxspltidp_constant_immediate (rtx op, machine_mode mode)
return ret;
}
-/* Return the constant that will go in the LXVKQ instruction. */
-
-/* LXVKQ immediates. */
-enum {
- LXVKQ_ONE = 1,
- LXVKQ_TWO = 2,
- LXVKQ_THREE = 3,
- LXVKQ_FOUR = 4,
- LXVKQ_FIVE = 5,
- LXVKQ_SIX = 6,
- LXVKQ_SEVEN = 7,
- LXVKQ_INF = 8,
- LXVKQ_NAN = 9,
- LXVKQ_NEG_ZERO = 16,
- LXVKQ_NEG_ONE = 17,
- LXVKQ_NEG_TWO = 18,
- LXVKQ_NEG_THREE = 19,
- LXVKQ_NEG_FOUR = 20,
- LXVKQ_NEG_FIVE = 21,
- LXVKQ_NEG_SIX = 22,
- LXVKQ_NEG_SEVEN = 23,
- LXVKQ_NEG_INF = 24
-};
-
-int
-lxvkq_constant_immediate (rtx op, machine_mode mode)
-{
- int ret = -1;
- gcc_assert (easy_fp_constant_ieee128 (op, mode));
-
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
-
- gcc_assert (!real_issignaling_nan (rv));
-
- /* Special values (infinity, nan, -0.0. */
- if (real_isinf (rv))
- ret = real_isneg (rv) ? LXVKQ_NEG_INF : LXVKQ_INF;
-
- /* Only recognize the normal NaN. Do not recognize NaNs with the negative
- sign, signaling NaNs, or NaNs that have non-zero mantissa. */
- else if (real_isnan (rv))
- {
- long w[4];
-
- real_to_target (&w[0], rv, mode);
- gcc_assert (BYTES_BIG_ENDIAN
- ? (w[0] == 0x7fff8000 && w[1] == 0 && w[2] == 0
- && w[3] == 0)
- : (w[3] == 0x7fff8000 && w[2] == 0 && w[1] == 0
- && w[0] == 0));
-
- ret = LXVKQ_NAN;
- }
-
- else if (real_isnegzero (rv))
- ret = LXVKQ_NEG_ZERO;
-
- else
- {
- HOST_WIDE_INT value = real_to_integer (rv);
- switch (value)
- {
- default:
- gcc_unreachable ();
-
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- ret = LXVKQ_ONE + (value - 1);
- break;
-
- case -1:
- case -2:
- case -3:
- case -4:
- case -5:
- case -6:
- case -7:
- ret = LXVKQ_NEG_ONE + (-value - 1);
- break;
- }
- }
-
- return ret;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -7141,12 +7051,6 @@ output_vec_const_move (rtx *operands)
return "xxspltidp %x0,%2";
}
- if (easy_fp_constant_ieee128 (vec, mode))
- {
- operands[2] = GEN_INT (lxvkq_constant_immediate (vec, mode));
- return "lxvkq %x0,%2";
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -13989,12 +13893,6 @@ rs6000_output_move_128bit (rtx operands[])
}
/* Constants. */
- else if (dest_vsx_p && easy_fp_constant_ieee128 (src, mode))
- {
- operands[2] = GEN_INT (lxvkq_constant_immediate (src, mode));
- return "lxvkq %x0,%2";
- }
-
else if (dest_regno >= 0
&& (CONST_INT_P (src)
|| CONST_WIDE_INT_P (src)
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index c9eb78952d6..1d7ce4cc94a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -644,10 +644,6 @@ mxxspltidp
Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
Generate (do not generate) XXSPLTIDP instructions.
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
-Generate (do not generate) LXVKQ instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d7e58654ded..fa33c9d9fbf 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1191,19 +1191,19 @@
;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move.
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
-;; XXSPLTIDP LXVKQ
+;; XXSPLTIDP
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
- wa, wa,
+ wa,
?&r, ??r, ??Y, <??r>, wa, v,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
- eV, eQ,
+ eV,
wQ, Y, r, r, wE, jwM,
?jwM, W, <nW>, v, wZ"))]
@@ -1215,44 +1215,44 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
- vecperm, vecperm,
+ vecperm,
store, load, store, *, vecsimple, vecsimple,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
- *, *,
+ *,
2, 2, 2, 2, *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
- *, *,
+ *,
2, 2, 2, 2, *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
- *, *,
+ *,
8, 8, 8, 8, *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10,
+ p10,
*, *, *, *, p9v, *,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIDP LXVKQ
+;; XXSPLTIDP
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, wa,
+ wa,
wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- eV, eQ,
+ eV,
wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
@@ -1264,17 +1264,17 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecperm, vecperm,
+ vecperm,
vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *,
+ *,
*, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10,
+ p10,
p9v, *, <VSisa>, *, *,
*, *")])
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 813d6316d8c..5035a3fd604 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3339,9 +3339,6 @@ A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction.
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eQ
-An IEEE 128-bit constant that can be loaded with the LXVKQ instruction.
-
@item eV
A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction.
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index 23ee7e85d84..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 18 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work070)] Revert patch.
@ 2021-10-04 21:44 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2021-10-04 21:44 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:81286cc3233bbe1c95473ce8aa95f68182a4ed33
commit 81286cc3233bbe1c95473ce8aa95f68182a4ed33
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Oct 4 17:43:35 2021 -0400
Revert patch.
2021-10-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/constraints.md (eW): New constraint.
* config/rs6000/predicates.md (easy_vector_constant_splat_word):
New predicate.
(easy_vector_constant): If we can use XXSPLTIW, the vector
constant is easy.
* config/rs6000/rs6000-protos.h (xxspltiw_constant_immediate): New
declaration.
* config/rs6000/rs6000.c (xxspltiw_constant_immediate): New
function.
(output_vec_const_move): Add support for loading up vector
constants with XXSPLTIW.
(prefixed_xxsplti_p): Recognize xxspltiw instructions as
prefixed.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
constants loaded with XXSPLTIW.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 5 -
gcc/config/rs6000/predicates.md | 104 ---------------------
gcc/config/rs6000/rs6000-protos.h | 1 -
gcc/config/rs6000/rs6000.c | 88 -----------------
gcc/config/rs6000/rs6000.opt | 5 -
gcc/config/rs6000/vsx.md | 28 +++---
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 ------
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 -------------
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ----------
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 ------------
10 files changed, 14 insertions(+), 424 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 46daeb0861c..1700657abe9 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -228,11 +228,6 @@
"An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
(match_operand 0 "easy_fp_constant_ieee128"))
-;; Vector constant that can be loaded with XXSPLTIW
-(define_constraint "eW"
- "A vector constant that can be loaded with the XXSPLTIW instruction."
- (match_operand 0 "easy_vector_constant_splat_word"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 78e64a8a1d4..30e89ec79f0 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -751,107 +751,6 @@
return easy_fp_constant_64bit_scalar (op, GET_MODE_INNER (mode));
})
-;; Return 1 if the operand is a constant that can be loaded with the XXSPLTIW
-;; instruction that loads up a 32-bit immediate and splats it into the vector.
-
-(define_predicate "easy_vector_constant_splat_word"
- (match_code "const_vector")
-{
- HOST_WIDE_INT value;
-
- if (!TARGET_PREFIXED || !TARGET_VSX || !TARGET_XXSPLTIW)
- return false;
-
- if (!CONST_VECTOR_P (op))
- return true;
-
- rtx element0 = CONST_VECTOR_ELT (op, 0);
-
- switch (mode)
- {
- /* V4SImode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case V4SImode:
- if (!CONST_VECTOR_DUPLICATE_P (op))
- return false;
-
- /* Don't return true if we can use the shorter vspltisw instruction. */
- value = INTVAL (element0);
- return (!EASY_VECTOR_15 (value));
-
- /* V4SFmode constant vectors that have the same element are
- can be used with XXSPLTIW. */
- case V4SFmode:
- if (!CONST_VECTOR_DUPLICATE_P (op))
- return false;
-
- /* Don't return true for 0.0f, since that can be created with
- xxspltib or xxlxor. */
- return (element0 != CONST0_RTX (SFmode));
-
- /* V8Hmode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case V8HImode:
- if (CONST_VECTOR_DUPLICATE_P (op))
- {
- /* Don't return true if we can use the shorter vspltish instruction. */
- value = INTVAL (element0);
- if (EASY_VECTOR_15 (value))
- return false;
-
- return true;
- }
-
- else
- {
- /* Check if all even elements are the same and all odd elements are
- the same. */
- rtx element1 = CONST_VECTOR_ELT (op, 1);
-
- if (!CONST_INT_P (element1))
- return false;
-
- for (size_t i = 2; i < GET_MODE_NUNITS (V8HImode); i += 2)
- if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1)))
- return false;
-
- return true;
- }
-
- /* V16QI constant vectors that have the first four elements identical to
- the next set of 4 elements, and so forth can generate XXSPLTIW. */
- case V16QImode:
- {
- /* If we can use XXSPLTIB, don't generate XXSPLTIW. */
- if (xxspltib_constant_nosplit (op, mode))
- return false;
-
- rtx element1 = CONST_VECTOR_ELT (op, 1);
- rtx element2 = CONST_VECTOR_ELT (op, 2);
- rtx element3 = CONST_VECTOR_ELT (op, 3);
-
- if (!CONST_INT_P (element0) || !CONST_INT_P (element1)
- || !CONST_INT_P (element2) || !CONST_INT_P (element3))
- return false;
-
- for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4)
- if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1))
- || !rtx_equal_p (element2, CONST_VECTOR_ELT (op, i + 2))
- || !rtx_equal_p (element3, CONST_VECTOR_ELT (op, i + 3)))
- return false;
-
- return true;
- }
-
- default:
- break;
- }
-
- return false;
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -972,9 +871,6 @@
if (easy_vector_constant_64bit_element (op, mode))
return true;
- if (easy_vector_constant_splat_word (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 540c401e7ad..a21fa08b367 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -33,7 +33,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern int easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
extern long xxspltidp_constant_immediate (rtx, machine_mode);
-extern long xxspltiw_constant_immediate (rtx, machine_mode);
extern int lxvkq_constant_immediate (rtx, machine_mode);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 79123f4e834..7b0b5357f0b 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -7000,82 +7000,6 @@ xxspltidp_constant_immediate (rtx op, machine_mode mode)
return ret;
}
-/* Return the immediate value used in the XXSPLTIW instruction. */
-long
-xxspltiw_constant_immediate (rtx op, machine_mode mode)
-{
- long ret;
-
- gcc_assert (easy_vector_constant_splat_word (op, mode));
-
- switch (mode)
- {
- default:
- gcc_unreachable ();
-
- /* V4SImode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case E_V4SImode:
- gcc_assert (CONST_VECTOR_DUPLICATE_P (op));
- ret = INTVAL (CONST_VECTOR_ELT (op, 0));
- break;
-
- /* V4SFmode constant vectors that have the same element are
- can be used with XXSPLTIW. */
- case E_V4SFmode:
- gcc_assert (CONST_VECTOR_DUPLICATE_P (op));
- ret = rs6000_const_f32_to_i32 (CONST_VECTOR_ELT (op, 0));
- break;
-
- /* V8HImode constant vectors with all of the even elements the same and
- all of the odd elements the same can used XXSPLTIW. */
- case E_V8HImode:
- {
- if (!rtx_equal_p (CONST_VECTOR_ELT (op, 0), CONST_VECTOR_ELT (op, 2))
- || !rtx_equal_p (CONST_VECTOR_ELT (op, 1), CONST_VECTOR_ELT (op, 3)))
- gcc_unreachable ();
-
- long value0 = INTVAL (CONST_VECTOR_ELT (op, 0)) & 0xffff;
- long value1 = INTVAL (CONST_VECTOR_ELT (op, 1)) & 0xffff;
-
- if (!BYTES_BIG_ENDIAN)
- std::swap (value0, value1);
-
- ret = (value0 << 16) | value1;
- }
- break;
-
- /* V16QI constant vectors that have the first four elements identical to
- the next set of 4 elements, and so forth can generate XXSPLTIW. */
- case E_V16QImode:
- {
- rtx op0 = CONST_VECTOR_ELT (op, 0);
- rtx op1 = CONST_VECTOR_ELT (op, 1);
- rtx op2 = CONST_VECTOR_ELT (op, 2);
- rtx op3 = CONST_VECTOR_ELT (op, 3);
-
- for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4)
- if (!rtx_equal_p (op0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (op1, CONST_VECTOR_ELT (op, i + 1))
- || !rtx_equal_p (op2, CONST_VECTOR_ELT (op, i + 2))
- || !rtx_equal_p (op3, CONST_VECTOR_ELT (op, i + 3)))
- gcc_unreachable ();
-
- long value0 = INTVAL (op0) & 0xff;
- long value1 = INTVAL (op1) & 0xff;
- long value2 = INTVAL (op2) & 0xff;
- long value3 = INTVAL (op3) & 0xff;
-
- ret = ((BYTES_BIG_ENDIAN)
- ? ((value0 << 24) | (value1 << 16) | (value2 << 8) | value3)
- : ((value3 << 24) | (value2 << 16) | (value1 << 8) | value0));
- }
- break;
- }
-
- return ret;
-}
-
/* Return the constant that will go in the LXVKQ instruction. */
/* LXVKQ immediates. */
@@ -7217,12 +7141,6 @@ output_vec_const_move (rtx *operands)
return "xxspltidp %x0,%2";
}
- if (easy_vector_constant_splat_word (vec, mode))
- {
- operands[2] = GEN_INT (xxspltiw_constant_immediate (vec, mode));
- return "xxspltiw %x0,%2";
- }
-
if (easy_fp_constant_ieee128 (vec, mode))
{
operands[2] = GEN_INT (lxvkq_constant_immediate (vec, mode));
@@ -26997,12 +26915,6 @@ prefixed_xxsplti_p (rtx_insn *insn)
case E_V2DFmode:
return easy_vector_constant_64bit_element (src, mode);
- case E_V16QImode:
- case E_V8HImode:
- case E_V4SImode:
- case E_V4SFmode:
- return easy_vector_constant_splat_word (src, mode);
-
default:
break;
}
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index a53aad72547..c9eb78952d6 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -644,11 +644,6 @@ mxxspltidp
Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
Generate (do not generate) XXSPLTIDP instructions.
-;; Do not enable at this time.
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(0) Save
-Generate (do not generate) XXSPLTIW instructions.
-
mlxvkq
Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
Generate (do not generate) LXVKQ instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 712e5df0c02..d7e58654ded 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1191,19 +1191,19 @@
;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move.
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
-;; XXSPLTIDP XXSPLTIW LXVKQ
+;; XXSPLTIDP LXVKQ
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
- wa, wa, wa,
+ wa, wa,
?&r, ??r, ??Y, <??r>, wa, v,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
- eV, eW, eQ,
+ eV, eQ,
wQ, Y, r, r, wE, jwM,
?jwM, W, <nW>, v, wZ"))]
@@ -1215,44 +1215,44 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
- vecperm, vecperm, vecperm,
+ vecperm, vecperm,
store, load, store, *, vecsimple, vecsimple,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
- *, *, *,
+ *, *,
2, 2, 2, 2, *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
- *, *, *,
+ *, *,
2, 2, 2, 2, *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
- *, *, *,
+ *, *,
8, 8, 8, 8, *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10,
+ p10, p10,
*, *, *, *, p9v, *,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIDP XXSPLTIW LXVKQ
+;; XXSPLTIDP LXVKQ
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, wa, wa,
+ wa, wa,
wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- eV, eW, eQ,
+ eV, eQ,
wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
@@ -1264,17 +1264,17 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecperm, vecperm, vecperm,
+ vecperm, vecperm,
vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
+ *, *,
*, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10,
+ p10, p10,
p9v, *, <VSisa>, *, *,
*, *")])
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
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