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From: Andrew Stubbs <ams@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r12-4222] amdgcn: Fix assembler version incompatibility
Date: Thu,  7 Oct 2021 10:32:12 +0000 (GMT)	[thread overview]
Message-ID: <20211007103212.BB0FE385802A@sourceware.org> (raw)

https://gcc.gnu.org/g:81c362c7c2bccd72d798bf7ea6c74d4b1cc3931f

commit r12-4222-g81c362c7c2bccd72d798bf7ea6c74d4b1cc3931f
Author: Andrew Stubbs <ams@codesourcery.com>
Date:   Thu Sep 30 17:50:33 2021 +0100

    amdgcn: Fix assembler version incompatibility
    
    This is another case of the global_load instruction format changing in LLVM
    (because they fixed a bug).  The configure test is already in place to detect
    what is needed.
    
    gcc/ChangeLog:
    
            * config/gcn/gcn-valu.md (gather<mode>_insn_2offsets<exec>): Apply
            HAVE_GCN_ASM_GLOBAL_LOAD_FIXED.
            (scatter<mode>_insn_2offsets<exec_scatter>): Likewise.

Diff:
---
 gcc/config/gcn/gcn-valu.md | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 84ff67508b9..01fdce64d42 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -827,8 +827,12 @@
 	/* Work around assembler bug in which a 64-bit register is expected,
 	but a 32-bit value would be correct.  */
 	int reg = REGNO (operands[2]) - FIRST_VGPR_REG;
-	sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;"
-		      "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc);
+	if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED)
+	  sprintf (buf, "global_load%%o0\t%%0, v%d, %%1 offset:%%3%s\;"
+			"s_waitcnt\tvmcnt(0)", reg, glc);
+	else
+	  sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;"
+			"s_waitcnt\tvmcnt(0)", reg, reg + 1, glc);
       }
     else
       gcc_unreachable ();
@@ -958,8 +962,12 @@
 	/* Work around assembler bug in which a 64-bit register is expected,
 	but a 32-bit value would be correct.  */
 	int reg = REGNO (operands[1]) - FIRST_VGPR_REG;
-	sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s",
-		 reg, reg + 1, glc);
+	if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED)
+	  sprintf (buf, "global_store%%s3\tv%d, %%3, %%0 offset:%%2%s",
+		   reg, glc);
+	else
+	  sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s",
+		   reg, reg + 1, glc);
       }
     else
       gcc_unreachable ();


                 reply	other threads:[~2021-10-07 10:32 UTC|newest]

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