[gcc r12-4241] Support reduc_{plus,smax,smin,umax,min}_scal_v4hi.

[gcc r12-4241] Support reduc_{plus,smax,smin,umax,min}_scal_v4hi.

[hongtao Liu]

https://gcc.gnu.org/g:77ca2cfcdcccee3c8e8aeaf1d03e9920893d2486

commit r12-4241-g77ca2cfcdcccee3c8e8aeaf1d03e9920893d2486
Author: liuhongt <hongtao.liu@intel.com>
Date:   Tue Sep 28 12:55:10 2021 +0800

    Support reduc_{plus,smax,smin,umax,min}_scal_v4hi.
    
    gcc/ChangeLog:
    
            PR target/102494
            * config/i386/i386-expand.c (emit_reduc_half): Hanlde V4HImode.
            * config/i386/mmx.md (reduc_plus_scal_v4hi): New.
            (reduc_<code>_scal_v4hi): New.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/i386/mmx-reduce-op-1.c: New test.
            * gcc.target/i386/mmx-reduce-op-2.c: New test.

Diff:
---
 gcc/config/i386/i386-expand.c                   |  5 +++
 gcc/config/i386/mmx.md                          | 36 +++++++++++++++
 gcc/testsuite/gcc.target/i386/mmx-reduce-op-1.c | 58 +++++++++++++++++++++++++
 gcc/testsuite/gcc.target/i386/mmx-reduce-op-2.c | 25 +++++++++++
 4 files changed, 124 insertions(+)

diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index 4780b993917..3e6f7d8ef7e 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -16043,6 +16043,11 @@ emit_reduc_half (rtx dest, rtx src, int i)
     case E_V2DFmode:
       tem = gen_vec_interleave_highv2df (dest, src, src);
       break;
+    case E_V4HImode:
+      d = gen_reg_rtx (V1DImode);
+      tem = gen_mmx_lshrv1di3 (d, gen_lowpart (V1DImode, src),
+			       GEN_INT (i / 2));
+      break;
     case E_V16QImode:
     case E_V8HImode:
     case E_V8HFmode:
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index c9467bc095a..106d41c8fd9 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -3965,6 +3965,42 @@
   DONE;
 })
 
+(define_expand "reduc_plus_scal_v4hi"
+ [(plus:V4HI
+    (match_operand:HI 0 "register_operand")
+    (match_operand:V4HI 1 "register_operand"))]
+ "TARGET_MMX_WITH_SSE"
+{
+  rtx tmp = gen_reg_rtx (V4HImode);
+  ix86_expand_reduc (gen_addv4hi3, tmp, operands[1]);
+  emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
+  DONE;
+})
+
+(define_expand "reduc_<code>_scal_v4hi"
+  [(smaxmin:V4HI
+     (match_operand:HI 0 "register_operand")
+     (match_operand:V4HI 1 "register_operand"))]
+  "TARGET_MMX_WITH_SSE"
+{
+  rtx tmp = gen_reg_rtx (V4HImode);
+  ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
+  emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
+  DONE;
+})
+
+(define_expand "reduc_<code>_scal_v4hi"
+  [(umaxmin:V4HI
+     (match_operand:HI 0 "register_operand")
+     (match_operand:V4HI 1 "register_operand"))]
+  "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
+{
+  rtx tmp = gen_reg_rtx (V4HImode);
+  ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
+  emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
+  DONE;
+})
+
 (define_expand "usadv8qi"
   [(match_operand:V2SI 0 "register_operand")
    (match_operand:V8QI 1 "register_operand")
diff --git a/gcc/testsuite/gcc.target/i386/mmx-reduce-op-1.c b/gcc/testsuite/gcc.target/i386/mmx-reduce-op-1.c
new file mode 100644
index 00000000000..ac20ed0d41f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/mmx-reduce-op-1.c
@@ -0,0 +1,58 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+/* { dg-final { scan-tree-dump-times "\.REDUC_PLUS" 1 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.REDUC_MIN" 2 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.REDUC_MAX" 2 "optimized" } } */
+
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define MIN(a, b) ((a) > (b) ? (b) : (a))
+
+short
+__attribute__((noipa, optimize("Ofast"),target("sse2")))
+reduce_add (short* __restrict pa)
+{
+  short sum = 0;
+  for (int i = 0; i != 4; i++)
+    sum += pa[i];
+  return sum;
+}
+
+short
+__attribute__((noipa, optimize("Ofast"),target("sse2")))
+reduce_smax (short* __restrict pa)
+{
+  short sum = pa[0];
+  for (int i = 0; i != 4; i++)
+    sum = MAX(sum, pa[i]);
+  return sum;
+}
+
+short
+__attribute__((noipa, optimize("Ofast"),target("sse2")))
+reduce_smin (short* __restrict pa)
+{
+  short sum = pa[0];
+  for (int i = 0; i != 4; i++)
+    sum = MIN(sum, pa[i]);
+  return sum;
+}
+
+unsigned short
+__attribute__((noipa, optimize("Ofast"),target("sse4.1")))
+reduce_umax (unsigned short* __restrict pa)
+{
+  unsigned short sum = pa[0];
+  for (int i = 0; i != 4; i++)
+    sum = MAX(sum, pa[i]);
+  return sum;
+}
+
+unsigned short
+__attribute__((noipa, optimize("Ofast"),target("sse4.1")))
+reduce_umin (unsigned short* __restrict pa)
+{
+  unsigned short sum = pa[0];
+  for (int i = 0; i != 4; i++)
+    sum = MIN(sum, pa[i]);
+  return sum;
+}
diff --git a/gcc/testsuite/gcc.target/i386/mmx-reduce-op-2.c b/gcc/testsuite/gcc.target/i386/mmx-reduce-op-2.c
new file mode 100644
index 00000000000..0896cd6d9be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/mmx-reduce-op-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { ! ia32 } } } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#include "mmx-reduce-op-1.c"
+
+static void
+sse4_1_test ()
+{
+  short p[4] = { -103, 23, 41, 200 };
+  unsigned short up[4] = { 100, 30, 299, 1000 };
+
+  if (reduce_add (p) != 161)
+    abort ();
+  if (reduce_smin (p) != -103)
+    abort ();
+  if (reduce_smax (p) != 200)
+    abort ();
+  if (reduce_umin (up) != 30)
+    abort ();
+  if (reduce_umax (up) != 1000)
+    abort();
+}