[gcc r12-4364] rs6000/test: Adjust test cases due to O2 vect [PR102658]

[gcc r12-4364] rs6000/test: Adjust test cases due to O2 vect [PR102658]

[Kewen Lin]

https://gcc.gnu.org/g:a124c1b0a2595f285c0d8ed863b37b83e14a6566

commit r12-4364-ga124c1b0a2595f285c0d8ed863b37b83e14a6566
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Wed Oct 13 00:20:45 2021 -0500

    rs6000/test: Adjust test cases due to O2 vect [PR102658]
    
    Commit r12-4240 enables vectorization at O2, this patch is to
    adjust some test cases for rs6000 port accordingly.
    
    It simply adds -fno-tree-vectorize to retain original test points.
    
    gcc/testsuite/ChangeLog:
    
            PR testsuite/102658
            * gcc.target/powerpc/dform-1.c: Adjust as vectorization enabled at O2.
            * gcc.target/powerpc/dform-2.c: Likewise.
            * gcc.target/powerpc/pr80510-2.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/powerpc/dform-1.c   | 4 +++-
 gcc/testsuite/gcc.target/powerpc/dform-2.c   | 4 +++-
 gcc/testsuite/gcc.target/powerpc/pr80510-2.c | 4 +++-
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/dform-1.c b/gcc/testsuite/gcc.target/powerpc/dform-1.c
index fac39230fd6..1a0b0cf4c34 100644
--- a/gcc/testsuite/gcc.target/powerpc/dform-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/dform-1.c
@@ -1,6 +1,8 @@
 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mpower9-vector -O2" } */
+/* Now O2 enables vectorization by default, which makes expected scalar
+   loads gone, so simply disable it.  */
+/* { dg-options "-mpower9-vector -O2 -fno-tree-vectorize" } */
 
 #ifndef TYPE
 #define TYPE double
diff --git a/gcc/testsuite/gcc.target/powerpc/dform-2.c b/gcc/testsuite/gcc.target/powerpc/dform-2.c
index 994733071e7..cc91f55b82d 100644
--- a/gcc/testsuite/gcc.target/powerpc/dform-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/dform-2.c
@@ -1,6 +1,8 @@
 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mpower9-vector -O2" } */
+/* Now O2 enables vectorization by default, which generates unexpected float
+   conversion for vector construction, so simply disable it.  */
+/* { dg-options "-mpower9-vector -O2 -fno-tree-vectorize" } */
 
 #ifndef TYPE
 #define TYPE float
diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c
index f85e005be64..d041d967c8b 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c
@@ -1,7 +1,9 @@
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+/* Now O2 enables vectorization by default, which generates unexpected VSR
+   to GPR movement for vector construction, so simply disable it.  */
+/* { dg-options "-mdejagnu-cpu=power8 -O2 -fno-tree-vectorize" } */
 
 /* Make sure that STXSSPX is generated for float scalars in Altivec registers
    on power7 instead of moving the value to a FPR register and doing a X-FORM