public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
From: Roger Sayle <sayle@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r12-4497] PR target/102785: Correct addsub/subadd patterns on bfin.
Date: Tue, 19 Oct 2021 10:02:31 +0000 (GMT) [thread overview]
Message-ID: <20211019100231.820F33858D3C@sourceware.org> (raw)
https://gcc.gnu.org/g:f98359ba9d3775319fb3181009be7d3dafe9ba15
commit r12-4497-gf98359ba9d3775319fb3181009be7d3dafe9ba15
Author: Roger Sayle <roger@nextmovesoftware.com>
Date: Tue Oct 19 11:00:10 2021 +0100
PR target/102785: Correct addsub/subadd patterns on bfin.
This patch resolves PR target/102785 where my recent patch to constant
fold saturating addition/subtraction exposed a latent bug in the bfin
backend. The patterns used for blackfin's V2HI ssaddsub and sssubadd
instructions had the indices/operations swapped. This was harmless
until we started evaluating these expressions at compile-time, when
the mismatch was caught by the testsuite.
2021-10-19 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR target/102785
* config/bfin/bfin.md (addsubv2hi3, subaddv2hi3, ssaddsubv2hi3,
sssubaddv2hi3): Swap the order of operators in vec_concat.
Diff:
---
gcc/config/bfin/bfin.md | 46 +++++++++++++++++++++++-----------------------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 8b311f3ab11..fd65f4d9e63 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -3016,19 +3016,6 @@
[(set_attr "type" "dsp32")])
(define_insn "addsubv2hi3"
- [(set (match_operand:V2HI 0 "register_operand" "=d")
- (vec_concat:V2HI
- (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
- (parallel [(const_int 0)])))
- (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
- ""
- "%0 = %1 +|- %2%!"
- [(set_attr "type" "dsp32")])
-
-(define_insn "subaddv2hi3"
[(set (match_operand:V2HI 0 "register_operand" "=d")
(vec_concat:V2HI
(minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
@@ -3038,23 +3025,23 @@
(plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
""
- "%0 = %1 -|+ %2%!"
+ "%0 = %1 +|- %2%!"
[(set_attr "type" "dsp32")])
-(define_insn "ssaddsubv2hi3"
+(define_insn "subaddv2hi3"
[(set (match_operand:V2HI 0 "register_operand" "=d")
(vec_concat:V2HI
- (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
- (parallel [(const_int 0)]))
- (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
- (parallel [(const_int 0)])))
- (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
- (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+ (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
+ (parallel [(const_int 0)]))
+ (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
+ (parallel [(const_int 0)])))
+ (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+ (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
""
- "%0 = %1 +|- %2 (S)%!"
+ "%0 = %1 -|+ %2%!"
[(set_attr "type" "dsp32")])
-(define_insn "sssubaddv2hi3"
+(define_insn "ssaddsubv2hi3"
[(set (match_operand:V2HI 0 "register_operand" "=d")
(vec_concat:V2HI
(ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
@@ -3064,6 +3051,19 @@
(ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
""
+ "%0 = %1 +|- %2 (S)%!"
+ [(set_attr "type" "dsp32")])
+
+(define_insn "sssubaddv2hi3"
+ [(set (match_operand:V2HI 0 "register_operand" "=d")
+ (vec_concat:V2HI
+ (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
+ (parallel [(const_int 0)]))
+ (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
+ (parallel [(const_int 0)])))
+ (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+ (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+ ""
"%0 = %1 -|+ %2 (S)%!"
[(set_attr "type" "dsp32")])
reply other threads:[~2021-10-19 10:02 UTC|newest]
Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211019100231.820F33858D3C@sourceware.org \
--to=sayle@gcc.gnu.org \
--cc=gcc-cvs@gcc.gnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).