[gcc r12-4497] PR target/102785: Correct addsub/subadd patterns on bfin.

[gcc r12-4497] PR target/102785: Correct addsub/subadd patterns on bfin.

[Roger Sayle]

https://gcc.gnu.org/g:f98359ba9d3775319fb3181009be7d3dafe9ba15

commit r12-4497-gf98359ba9d3775319fb3181009be7d3dafe9ba15
Author: Roger Sayle <roger@nextmovesoftware.com>
Date:   Tue Oct 19 11:00:10 2021 +0100

    PR target/102785: Correct addsub/subadd patterns on bfin.
    
    This patch resolves PR target/102785 where my recent patch to constant
    fold saturating addition/subtraction exposed a latent bug in the bfin
    backend.  The patterns used for blackfin's V2HI ssaddsub and sssubadd
    instructions had the indices/operations swapped.  This was harmless
    until we started evaluating these expressions at compile-time, when
    the mismatch was caught by the testsuite.
    
    2021-10-19  Roger Sayle  <roger@nextmovesoftware.com>
    
    gcc/ChangeLog
            PR target/102785
            * config/bfin/bfin.md (addsubv2hi3, subaddv2hi3, ssaddsubv2hi3,
            sssubaddv2hi3):  Swap the order of operators in vec_concat.

Diff:
---
 gcc/config/bfin/bfin.md | 46 +++++++++++++++++++++++-----------------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 8b311f3ab11..fd65f4d9e63 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -3016,19 +3016,6 @@
   [(set_attr "type" "dsp32")])
 
 (define_insn "addsubv2hi3"
-  [(set (match_operand:V2HI 0 "register_operand" "=d")
-	(vec_concat:V2HI
-	 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
-				 (parallel [(const_int 0)]))
-		  (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
-				 (parallel [(const_int 0)])))
-	 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
-		   (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
-  ""
-  "%0 = %1 +|- %2%!"
-  [(set_attr "type" "dsp32")])
-
-(define_insn "subaddv2hi3"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
 	(vec_concat:V2HI
 	 (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
@@ -3038,23 +3025,23 @@
 	 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
 		  (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
   ""
-  "%0 = %1 -|+ %2%!"
+  "%0 = %1 +|- %2%!"
   [(set_attr "type" "dsp32")])
 
-(define_insn "ssaddsubv2hi3"
+(define_insn "subaddv2hi3"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
 	(vec_concat:V2HI
-	 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
-				    (parallel [(const_int 0)]))
-		     (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
-				    (parallel [(const_int 0)])))
-	 (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
-		      (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+	 (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
+				 (parallel [(const_int 0)]))
+		  (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
+				 (parallel [(const_int 0)])))
+	 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+		   (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
   ""
-  "%0 = %1 +|- %2 (S)%!"
+  "%0 = %1 -|+ %2%!"
   [(set_attr "type" "dsp32")])
 
-(define_insn "sssubaddv2hi3"
+(define_insn "ssaddsubv2hi3"
   [(set (match_operand:V2HI 0 "register_operand" "=d")
 	(vec_concat:V2HI
 	 (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
@@ -3064,6 +3051,19 @@
 	 (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
 		     (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
   ""
+  "%0 = %1 +|- %2 (S)%!"
+  [(set_attr "type" "dsp32")])
+
+(define_insn "sssubaddv2hi3"
+  [(set (match_operand:V2HI 0 "register_operand" "=d")
+	(vec_concat:V2HI
+	 (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")
+				    (parallel [(const_int 0)]))
+		     (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")
+				    (parallel [(const_int 0)])))
+	 (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+		      (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]
+  ""
   "%0 = %1 -|+ %2 (S)%!"
   [(set_attr "type" "dsp32")])