[gcc r12-4569] AArch64: Tune case-values-threshold

[gcc r12-4569] AArch64: Tune case-values-threshold

[Wilco Dijkstra]

https://gcc.gnu.org/g:9c751b88def09f71e1edbf623d41776478ead6fd

commit r12-4569-g9c751b88def09f71e1edbf623d41776478ead6fd
Author: Wilco Dijkstra <wdijkstr@arm.com>
Date:   Wed Oct 20 13:16:54 2021 +0100

    AArch64: Tune case-values-threshold
    
    Tune the case-values-threshold setting for modern cores.  A value of 11 improves
    SPECINT2017 by 0.2% and reduces codesize by 0.04%.  With -Os use value 8 which
    reduces codesize by 0.07%.
    
    2021-10-18  Wilco Dijkstra  <wdijkstr@arm.com>
    
    gcc/
            * config/aarch64/aarch64.c (aarch64_case_values_threshold):
            Change to 8 with -Os, 11 otherwise.

Diff:
---
 gcc/config/aarch64/aarch64.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 1d53c714ecd..674edd4e305 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -9500,8 +9500,8 @@ aarch64_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
    The expansion for a table switch is quite expensive due to the number
    of instructions, the table lookup and hard to predict indirect jump.
    When optimizing for speed, and -O3 enabled, use the per-core tuning if 
-   set, otherwise use tables for > 16 cases as a tradeoff between size and
-   performance.  When optimizing for size, use the default setting.  */
+   set, otherwise use tables for >= 11 cases as a tradeoff between size and
+   performance.  When optimizing for size, use 8 for smallest codesize.  */
 
 static unsigned int
 aarch64_case_values_threshold (void)
@@ -9512,7 +9512,7 @@ aarch64_case_values_threshold (void)
       && selected_cpu->tune->max_case_values != 0)
     return selected_cpu->tune->max_case_values;
   else
-    return optimize_size ? default_case_values_threshold () : 17;
+    return optimize_size ? 8 : 11;
 }
 
 /* Return true if register REGNO is a valid index register.