[gcc r12-4579] AArch64: Combine cmeq 0 + not into cmtst

[gcc r12-4579] AArch64: Combine cmeq 0 + not into cmtst

[Tamar Christina]

https://gcc.gnu.org/g:3db4440d4c79f0a21c6574482c85bbd44a9fd8a6

commit r12-4579-g3db4440d4c79f0a21c6574482c85bbd44a9fd8a6
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Wed Oct 20 17:11:52 2021 +0100

    AArch64: Combine cmeq 0 + not into cmtst
    
    This turns a bitwise inverse of an equality comparison with 0 into a compare of
    bitwise nonzero (cmtst).
    
    We already have one pattern for cmsts, this adds an additional one which does
    not require an additional bitwise and.
    
    i.e.
    
    #include <arm_neon.h>
    
    uint8x8_t bar(int16x8_t abs_row0, int16x8_t row0) {
      uint16x8_t row0_diff =
        vreinterpretq_u16_s16(veorq_s16(abs_row0, vshrq_n_s16(row0, 15)));
      uint8x8_t abs_row0_gt0 =
        vmovn_u16(vcgtq_u16(vreinterpretq_u16_s16(abs_row0), vdupq_n_u16(0)));
      return abs_row0_gt0;
    }
    
    now generates:
    
    bar:
            cmtst   v0.8h, v0.8h, v0.8h
            xtn     v0.8b, v0.8h
            ret
    
    instead of:
    
    bar:
            cmeq    v0.8h, v0.8h, #0
            not     v0.16b, v0.16b
            xtn     v0.8b, v0.8h
            ret
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64-simd.md (*aarch64_cmtst_same_<mode>): New.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/aarch64/mvn-cmeq0-1.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-simd.md             | 17 +++++++++++++++++
 gcc/testsuite/gcc.target/aarch64/mvn-cmeq0-1.c | 17 +++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index b0dda554466..29f381728a3 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -6620,6 +6620,23 @@
   [(set_attr "type" "neon_tst<q>")]
 )
 
+;; One can also get a cmtsts by having to combine a
+;; not (neq (eq x 0)) in which case you rewrite it to
+;; a comparison against itself
+
+(define_insn "*aarch64_cmtst_same_<mode>"
+  [(set (match_operand:<V_INT_EQUIV> 0 "register_operand" "=w")
+	(plus:<V_INT_EQUIV>
+	  (eq:<V_INT_EQUIV>
+	    (match_operand:VDQ_I 1 "register_operand" "w")
+	    (match_operand:VDQ_I 2 "aarch64_simd_imm_zero"))
+	  (match_operand:<V_INT_EQUIV> 3 "aarch64_simd_imm_minus_one")))
+  ]
+  "TARGET_SIMD"
+  "cmtst\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>1<Vmtype>"
+  [(set_attr "type" "neon_tst<q>")]
+)
+
 (define_insn_and_split "aarch64_cmtstdi"
   [(set (match_operand:DI 0 "register_operand" "=w,r")
 	(neg:DI
diff --git a/gcc/testsuite/gcc.target/aarch64/mvn-cmeq0-1.c b/gcc/testsuite/gcc.target/aarch64/mvn-cmeq0-1.c
new file mode 100644
index 00000000000..27b3909ca91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mvn-cmeq0-1.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble } */
+/* { dg-options "-O --save-temps" } */
+
+#include <arm_neon.h>
+
+uint8x8_t bar(int16x8_t abs_row0, int16x8_t row0) {
+  uint16x8_t row0_diff =
+    vreinterpretq_u16_s16(veorq_s16(abs_row0, vshrq_n_s16(row0, 15)));
+  uint8x8_t abs_row0_gt0 =
+    vmovn_u16(vcgtq_u16(vreinterpretq_u16_s16(abs_row0), vdupq_n_u16(0)));
+  return abs_row0_gt0;
+}
+
+
+/* { dg-final { scan-assembler-times {\tcmtst\t} 1 } } */
+/* { dg-final { scan-assembler-not {\tcmeq\t} } } */
+/* { dg-final { scan-assembler-not {\tnot\t} } } */