[gcc r12-4663] AArch64 testsuite: Force shrn-combine-*.c to use NEON.

[gcc r12-4663] AArch64 testsuite: Force shrn-combine-*.c to use NEON.

[Tamar Christina]

https://gcc.gnu.org/g:2cbfaba60661ebbdfcffe725ab55fbb323e2a187

commit r12-4663-g2cbfaba60661ebbdfcffe725ab55fbb323e2a187
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Mon Oct 25 15:14:04 2021 +0100

    AArch64 testsuite: Force shrn-combine-*.c to use NEON.
    
    These tests are testing Advanced SIMD codegen, so if the compiler or the
    testsuite is forcing SVE they will fail.
    
    This adds +nosve so that we always generate Advanced SIMD codegen.
    
    gcc/testsuite/ChangeLog:
    
            PR target/102907
            * gcc.target/aarch64/shrn-combine-1.c: Disable SVE.
            * gcc.target/aarch64/shrn-combine-2.c: Likewise.
            * gcc.target/aarch64/shrn-combine-3.c: Likewise.
            * gcc.target/aarch64/shrn-combine-4.c: Likewise.
            * gcc.target/aarch64/shrn-combine-5.c: Likewise.
            * gcc.target/aarch64/shrn-combine-6.c: Likewise.
            * gcc.target/aarch64/shrn-combine-7.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c | 2 ++
 gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c | 2 ++
 gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c | 2 ++
 gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c | 2 ++
 gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c | 2 ++
 gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c | 2 ++
 gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c | 2 ++
 7 files changed, 14 insertions(+)

diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c
index a28524662ed..334e94aa76e 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE char
 
 void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n)
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c
index 012135b424f..c90de72e9c3 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE short
 
 void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n)
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c
index 8b5b360de62..a05ecbb373a 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE int
 
 void foo (unsigned long long * restrict a, TYPE * restrict d, int n)
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c
index fedca7621e2..36ebab7b742 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE long long
 
 void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n)
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c
index 408e8553578..973e577e938 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE1 char
 #define TYPE2 short
 #define SHIFT 8
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c
index 6211ba3e41c..db36a9c4218 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE1 short
 #define TYPE2 int
 #define SHIFT 16
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c
index 56cbeacc6de..e7caf3c7587 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE1 int
 #define TYPE2 long long
 #define SHIFT 32