[gcc r12-5002] powerpc: Fix vsx_splat_v4si_di breakage on Power8.

[gcc r12-5002] powerpc: Fix vsx_splat_v4si_di breakage on Power8.

[David Edelsohn]

https://gcc.gnu.org/g:a7dce7626a6d5247d7dda48fa36d3cdc258aae84

commit r12-5002-ga7dce7626a6d5247d7dda48fa36d3cdc258aae84
Author: David Edelsohn <dje.gcc@gmail.com>
Date:   Mon Nov 8 11:46:47 2021 -0500

    powerpc: Fix vsx_splat_v4si_di breakage on Power8.
    
    The vsx_splat_v4si_di pattern uses a Power8 and a Power9 instruction.
    The final condition of TARGET_DIRECT_MODE_64BIT implicitly requires Power8.
    The "we" constraint requires Power9, but also requires 64 bit. Because
    the DImode pattern already requires 64 bit mode, this isn't horrible,
    but it would be best to remove all uses of "we" constraint.  The
    mtvsrws instruction itself does not require 64 bit mode.
    
    This patch reverts the previous change to fix the breakage.
    
    gcc/ChangeLog:
    
            * config/rs6000/vsx.md (vsx_splat_v4si_di): Revert "wa"
            constraint to "we".

Diff:
---
 gcc/config/rs6000/vsx.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a97f7f2a680..83d6c7b76f3 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4578,7 +4578,7 @@
 ;; allows us to use direct move to get the value in a vector register
 ;; so that we can use XXSPLTW
 (define_insn "vsx_splat_v4si_di"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
+  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,we")
 	(vec_duplicate:V4SI
 	 (truncate:SI
 	  (match_operand:DI 1 "gpc_reg_operand" "wa,r"))))]