[gcc r12-5800] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class.

[gcc r12-5800] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class.

[hongtao Liu]

https://gcc.gnu.org/g:d1011a41efd121ede2f427c1dffd6ac62f92962e

commit r12-5800-gd1011a41efd121ede2f427c1dffd6ac62f92962e
Author: liuhongt <hongtao.liu@intel.com>
Date:   Tue Nov 30 13:50:11 2021 +0800

    Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class.
    
    When moves between integer and sse registers are cheap.
    
    2021-12-06  Hongtao Liu  <Hongtao.liu@intel.com>
                Uroš Bizjak  <ubizjak@gmail.com>
    gcc/ChangeLog:
    
            PR target/95740
            * config/i386/i386.c (ix86_preferred_reload_class): Allow
            integer regs when moves between register units are cheap.
            * config/i386/i386.h (INT_SSE_CLASS_P): New.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/i386/pr95740.c: New test.

Diff:
---
 gcc/config/i386/i386.c                  | 12 ++++++++++--
 gcc/config/i386/i386.h                  |  2 ++
 gcc/testsuite/gcc.target/i386/pr95740.c | 26 ++++++++++++++++++++++++++
 3 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ccb57afee05..52547b0f057 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -19214,9 +19214,17 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
       return NO_REGS;
     }
 
-  /* Prefer SSE regs only, if we can use them for math.  */
+  /* Prefer SSE if we can use them for math.  Also allow integer regs
+     when moves between register units are cheap.  */
   if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
-    return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
+    {
+      if (TARGET_INTER_UNIT_MOVES_FROM_VEC
+	  && TARGET_INTER_UNIT_MOVES_TO_VEC
+	  && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (word_mode))
+	return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS;
+      else
+	return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
+    }
 
   /* Generally when we see PLUS here, it's the function invariant
      (plus soft-fp const_int).  Which can only be computed into general
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 4f70085d793..46fdd6e1088 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1279,6 +1279,8 @@ enum reg_class
   reg_class_subset_p ((CLASS), FLOAT_REGS)
 #define SSE_CLASS_P(CLASS) \
   reg_class_subset_p ((CLASS), ALL_SSE_REGS)
+#define INT_SSE_CLASS_P(CLASS) \
+  reg_class_subset_p ((CLASS), INT_SSE_REGS)
 #define MMX_CLASS_P(CLASS) \
   ((CLASS) == MMX_REGS)
 #define MASK_CLASS_P(CLASS) \
diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c
new file mode 100644
index 00000000000..7ecd71ba8c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95740.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-msse2 -O2 -mtune=generic -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */
+/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */
+
+int
+foo (float a)
+{
+  union{
+    int b;
+    float a;}u;
+  u.a = a;
+  return u.b + 1;
+}
+
+long long
+foo1 (double a)
+{
+  union{
+    long long b;
+    double a;}u;
+  u.a = a;
+  return u.b + 1;
+}