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From: Uros Bizjak <uros@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-6194] i386: Always enable mov<V_32:mode> patterns [PR103894] Date: Mon, 3 Jan 2022 19:59:34 +0000 (GMT) [thread overview] Message-ID: <20220103195934.322BF3858C2C@sourceware.org> (raw) https://gcc.gnu.org/g:1096ab1775636f35de9c6661f8f71f03299af998 commit r12-6194-g1096ab1775636f35de9c6661f8f71f03299af998 Author: Uros Bizjak <ubizjak@gmail.com> Date: Mon Jan 3 20:58:16 2022 +0100 i386: Always enable mov<V_32:mode> patterns [PR103894] Middle end tries to generate V4QImode moves to implement V2QImode inserts and calls emit_move_multi_word when V4QImode moves are unavailable, as is the case with 32-bit vector moves, constrainted with TARGET_SSE2. However, this triggers gcc_assert (mode_size >= UNITS_PER_WORD); in emit_move_multi_word, since mode_size of V4QImode operand is less than UNITS_PER_WORD of 64-bit targets. The patch unconditionally enables 32-bit vector moves to match 16-bit vector moves. This also enables implementation of 32-bit vector logic operations with GPR in a follow-up patch. 2022-01-03 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/103894 * config/i386/mmx.md (mov<V_32:mode>): Remove TARGET_SSE2 constraint. (mov<V_32:mode>_internal): Ditto. (*push<V_32:mode>_rex64): Ditto. (movmisalign<V_32:mode>): Ditto. (*push<V_32:mode>_rex64 splitter): Enable for TARGET_64BIT && TARGET_SSE. (*push<V_32:mode>2): Remove insn pattern. gcc/testsuite/ChangeLog: PR target/103894 * gcc.target/i386/pr103894.c: New test. Diff: --- gcc/config/i386/mmx.md | 23 ++++++----------------- gcc/testsuite/gcc.target/i386/pr103894.c | 13 +++++++++++++ 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 67b02661243..5b33d3cfc1c 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -250,7 +250,7 @@ (define_expand "mov<mode>" [(set (match_operand:V_32 0 "nonimmediate_operand") (match_operand:V_32 1 "nonimmediate_operand"))] - "TARGET_SSE2" + "" { ix86_expand_vector_move (<MODE>mode, operands); DONE; @@ -261,8 +261,7 @@ "=r ,m ,v,v,v,m,r,v") (match_operand:V_32 1 "general_operand" "rmC,rC,C,v,m,v,v,r"))] - "TARGET_SSE2 - && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "!(MEM_P (operands[0]) && MEM_P (operands[1]))" { switch (get_attr_type (insn)) { @@ -321,29 +320,19 @@ (define_insn "*push<mode>2_rex64" [(set (match_operand:V_32 0 "push_operand" "=X,X") (match_operand:V_32 1 "nonmemory_no_elim_operand" "rC,*v"))] - "TARGET_SSE2 && TARGET_64BIT" + "TARGET_64BIT" "@ push{q}\t%q1 #" [(set_attr "type" "push,multi") (set_attr "mode" "DI")]) -(define_insn "*push<mode>2" - [(set (match_operand:V_32 0 "push_operand" "=<,<") - (match_operand:V_32 1 "general_no_elim_operand" "rC*m,*v"))] - "TARGET_SSE2 && !TARGET_64BIT" - "@ - push{l}\t%1 - #" - [(set_attr "type" "push,multi") - (set_attr "mode" "SI")]) - (define_split [(set (match_operand:V_32 0 "push_operand") (match_operand:V_32 1 "sse_reg_operand"))] - "TARGET_SSE2 && reload_completed" + "TARGET_64BIT && TARGET_SSE && reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) - (set (match_dup 0) (match_dup 1))] + (set (match_dup 0) (match_dup 1))] { operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (<V_32:MODE>mode))); /* Preserve memory attributes. */ @@ -353,7 +342,7 @@ (define_expand "movmisalign<mode>" [(set (match_operand:V_32 0 "nonimmediate_operand") (match_operand:V_32 1 "nonimmediate_operand"))] - "TARGET_SSE2" + "" { ix86_expand_vector_move (<MODE>mode, operands); DONE; diff --git a/gcc/testsuite/gcc.target/i386/pr103894.c b/gcc/testsuite/gcc.target/i386/pr103894.c new file mode 100644 index 00000000000..69c81046930 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103894.c @@ -0,0 +1,13 @@ +/* PR target/103894 */ +/* { dg-do compile } */ +/* { dg-options "-msse -mno-sse2" } */ + +typedef unsigned char __attribute__((__vector_size__ (32))) V; +typedef unsigned char __attribute__((__vector_size__ (2))) W; + +V v; + +W foo (W w) +{ + return __builtin_shufflevector (v, w, 3, 4); +}
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