public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: Add GENERAL_AND_VPR_REGS regclass
@ 2022-01-12 8:27 Christophe Lyon
0 siblings, 0 replies; 5+ messages in thread
From: Christophe Lyon @ 2022-01-12 8:27 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ffdfb751f19947027c3f3226e8d43bd11565ad6f
commit ffdfb751f19947027c3f3226e8d43bd11565ad6f
Author: Christophe Lyon <christophe.lyon@foss.st.com>
Date: Wed Oct 13 09:16:09 2021 +0000
arm: Add GENERAL_AND_VPR_REGS regclass
At some point during the development of this patch series, it appeared
that in some cases the register allocator wants “VPR or general”
rather than “VPR or general or FP” (which is the same thing as
ALL_REGS). The series does not seem to require this anymore, but it
seems to be a good thing to do anyway, to give the register allocator
more freedom.
2021-10-13 Christophe Lyon <christophe.lyon@foss.st.com>
gcc/
* config/arm/arm.h (reg_class): Add GENERAL_AND_VPR_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
Diff:
---
gcc/config/arm/arm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 3a8d223ee62..08b858effd8 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1287,6 +1287,7 @@ enum reg_class
SFP_REG,
AFP_REG,
VPR_REG,
+ GENERAL_AND_VPR_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1316,6 +1317,7 @@ enum reg_class
"SFP_REG", \
"AFP_REG", \
"VPR_REG", \
+ "GENERAL_AND_VPR_REGS", \
"ALL_REGS" \
}
@@ -1344,6 +1346,7 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \
+ { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \
{ 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \
}
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: Add GENERAL_AND_VPR_REGS regclass
@ 2022-02-22 9:07 Christophe Lyon
0 siblings, 0 replies; 5+ messages in thread
From: Christophe Lyon @ 2022-02-22 9:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:699e0457fcab43a7f557bac6d93b5002049b6c03
commit 699e0457fcab43a7f557bac6d93b5002049b6c03
Author: Christophe Lyon <christophe.lyon@foss.st.com>
Date: Wed Oct 13 09:16:09 2021 +0000
arm: Add GENERAL_AND_VPR_REGS regclass
At some point during the development of this patch series, it appeared
that in some cases the register allocator wants “VPR or general”
rather than “VPR or general or FP” (which is the same thing as
ALL_REGS). The series does not seem to require this anymore, but it
seems to be a good thing to do anyway, to give the register allocator
more freedom.
CLASS_MAX_NREGS and arm_hard_regno_nregs need adjustment to avoid a
regression in gcc.dg/stack-usage-1.c when compiled with -mthumb
-mfloat-abi=hard -march=armv8.1-m.main+mve.fp+fp.dp.
2022-01-13 Christophe Lyon <christophe.lyon@foss.st.com>
gcc/
* config/arm/arm.h (reg_class): Add GENERAL_AND_VPR_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(CLASS_MAX_NREGS): Handle VPR.
* config/arm/arm.c (arm_hard_regno_nregs): Handle VPR.
Diff:
---
gcc/config/arm/arm.c | 3 +++
gcc/config/arm/arm.h | 7 ++++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index bb75921f32d..c3559ca8703 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -25287,6 +25287,9 @@ thumb2_asm_output_opcode (FILE * stream)
static unsigned int
arm_hard_regno_nregs (unsigned int regno, machine_mode mode)
{
+ if (IS_VPR_REGNUM (regno))
+ return CEIL (GET_MODE_SIZE (mode), 2);
+
if (TARGET_32BIT
&& regno > PC_REGNUM
&& regno != FRAME_POINTER_REGNUM
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index dacce2b7f08..2416fb5ef64 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1287,6 +1287,7 @@ enum reg_class
SFP_REG,
AFP_REG,
VPR_REG,
+ GENERAL_AND_VPR_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1316,6 +1317,7 @@ enum reg_class
"SFP_REG", \
"AFP_REG", \
"VPR_REG", \
+ "GENERAL_AND_VPR_REGS", \
"ALL_REGS" \
}
@@ -1344,6 +1346,7 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \
+ { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \
{ 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \
}
@@ -1453,7 +1456,9 @@ extern const char *fp_sysreg_names[NB_FP_SYSREGS];
ARM regs are UNITS_PER_WORD bits.
FIXME: Is this true for iWMMX? */
#define CLASS_MAX_NREGS(CLASS, MODE) \
- (ARM_NUM_REGS (MODE))
+ (CLASS == VPR_REG) \
+ ? CEIL (GET_MODE_SIZE (MODE), 2) \
+ : (ARM_NUM_REGS (MODE))
/* If defined, gives a class of registers that cannot be used as the
operand of a SUBREG that changes the mode of the object illegally. */
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: Add GENERAL_AND_VPR_REGS regclass
@ 2021-11-16 14:06 Christophe Lyon
0 siblings, 0 replies; 5+ messages in thread
From: Christophe Lyon @ 2021-11-16 14:06 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:38ae70f812ece31e678a73348c58f4c068daa9bc
commit 38ae70f812ece31e678a73348c58f4c068daa9bc
Author: Christophe Lyon <christophe.lyon@foss.st.com>
Date: Wed Oct 13 09:16:09 2021 +0000
arm: Add GENERAL_AND_VPR_REGS regclass
At some point during the development of this patch series, it appeared
that in some cases the register allocator wants “VPR or general”
rather than “VPR or general or FP” (which is the same thing as
ALL_REGS). The series does not seem to require this anymore, but it
seems to be a good thing to do anyway, to give the register allocator
more freedom.
2021-10-13 Christophe Lyon <christophe.lyon@foss.st.com>
gcc/
* config/arm/arm.h (reg_class): Add GENERAL_AND_VPR_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
Diff:
---
gcc/config/arm/arm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 015299c1534..eae1b1cd0fb 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1286,6 +1286,7 @@ enum reg_class
SFP_REG,
AFP_REG,
VPR_REG,
+ GENERAL_AND_VPR_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1315,6 +1316,7 @@ enum reg_class
"SFP_REG", \
"AFP_REG", \
"VPR_REG", \
+ "GENERAL_AND_VPR_REGS", \
"ALL_REGS" \
}
@@ -1343,6 +1345,7 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \
+ { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \
{ 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \
}
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: Add GENERAL_AND_VPR_REGS regclass
@ 2021-10-01 14:37 Christophe Lyon
0 siblings, 0 replies; 5+ messages in thread
From: Christophe Lyon @ 2021-10-01 14:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:c57fb3fc853d8bf04f589682f03e9d3baac2dbd5
commit c57fb3fc853d8bf04f589682f03e9d3baac2dbd5
Author: Christophe Lyon <christophe.lyon@foss.st.com>
Date: Thu Aug 26 16:01:58 2021 +0000
arm: Add GENERAL_AND_VPR_REGS regclass
At some point during the development of this patch series, it appeared
that in some cases the register allocator wants “VPR or general”
rather than “VPR or general or FP” (which is the same thing as
ALL_REGS). The series does not seem to require this anymore, but it
seems to be a good thing to do anyway, to give the register allocator
more freedom.
2021-09-01 Christophe Lyon <christophe.lyon@foss.st.com>
gcc/
* config/arm/arm.h (reg_class): Add GENERAL_AND_VPR_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
Diff:
---
gcc/config/arm/arm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 015299c1534..eae1b1cd0fb 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1286,6 +1286,7 @@ enum reg_class
SFP_REG,
AFP_REG,
VPR_REG,
+ GENERAL_AND_VPR_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1315,6 +1316,7 @@ enum reg_class
"SFP_REG", \
"AFP_REG", \
"VPR_REG", \
+ "GENERAL_AND_VPR_REGS", \
"ALL_REGS" \
}
@@ -1343,6 +1345,7 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \
+ { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \
{ 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \
}
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/clyon/heads/mve-autovec)] arm: Add GENERAL_AND_VPR_REGS regclass
@ 2021-09-29 7:30 Christophe Lyon
0 siblings, 0 replies; 5+ messages in thread
From: Christophe Lyon @ 2021-09-29 7:30 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d46ef2c9d143989e96d312e317c236c818210c34
commit d46ef2c9d143989e96d312e317c236c818210c34
Author: Christophe Lyon <christophe.lyon@foss.st.com>
Date: Thu Aug 26 16:01:58 2021 +0000
arm: Add GENERAL_AND_VPR_REGS regclass
At some point during the development of this patch series, it appeared
that in some cases the register allocator wants “VPR or general”
rather than “VPR or general or FP” (which is the same thing as
ALL_REGS). The series does not seem to require this anymore, but it
seems to be a good thing to do anyway, to give the register allocator
more freedom.
2021-09-01 Christophe Lyon <christophe.lyon@foss.st.com>
gcc/
* config/arm/arm.h (reg_class): Add GENERAL_AND_VPR_REGS.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
Diff:
---
gcc/config/arm/arm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 015299c1534..eae1b1cd0fb 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1286,6 +1286,7 @@ enum reg_class
SFP_REG,
AFP_REG,
VPR_REG,
+ GENERAL_AND_VPR_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1315,6 +1316,7 @@ enum reg_class
"SFP_REG", \
"AFP_REG", \
"VPR_REG", \
+ "GENERAL_AND_VPR_REGS", \
"ALL_REGS" \
}
@@ -1343,6 +1345,7 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \
+ { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \
{ 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \
}
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-02-22 9:07 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-12 8:27 [gcc(refs/users/clyon/heads/mve-autovec)] arm: Add GENERAL_AND_VPR_REGS regclass Christophe Lyon
-- strict thread matches above, loose matches on Subject: below --
2022-02-22 9:07 Christophe Lyon
2021-11-16 14:06 Christophe Lyon
2021-10-01 14:37 Christophe Lyon
2021-09-29 7:30 Christophe Lyon
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).