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* [gcc r12-6537] rs6000: Add split pattern to replace
@ 2022-01-13 3:06 Xiong Hu Luo
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From: Xiong Hu Luo @ 2022-01-13 3:06 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:080a06fcb076b3586ee4b00d415ae177f0b76b18
commit r12-6537-g080a06fcb076b3586ee4b00d415ae177f0b76b18
Author: Xionghu Luo <luoxhu@linux.ibm.com>
Date: Wed Jan 12 18:36:54 2022 -0600
rs6000: Add split pattern to replace
7: r120:V4SI=const_vector
8: r121:V4SI=unspec[r120:V4SI,r120:V4SI,0xc] 260
with r121:v4SI = r120:V4SI when r120 is a vector with same element.
gcc/ChangeLog:
* config/rs6000/altivec.md (sldoi_to_mov<mode>): New.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/sldoi_to_mov.c: New test.
Diff:
---
gcc/config/rs6000/altivec.md | 11 +++++++++++
gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c | 15 +++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 950b17862c4..d7e93f2b0c6 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -383,6 +383,17 @@
}
})
+(define_insn_and_split "sldoi_to_mov<mode>"
+ [(set (match_operand:VM 0 "altivec_register_operand")
+ (unspec:VM [(match_operand:VM 1 "easy_vector_constant")
+ (match_dup 1)
+ (match_operand:QI 2 "u5bit_cint_operand")]
+ UNSPEC_VSLDOI))]
+ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(set (match_dup 0) (match_dup 1))])
+
(define_insn "get_vrsave_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(reg:SI VRSAVE_REGNO)] UNSPEC_GET_VRSAVE))]
diff --git a/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c b/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c
new file mode 100644
index 00000000000..2053243c456
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include <altivec.h>
+vector signed int foo1 (vector signed int a) {
+ vector signed int b = {0};
+ return vec_sum2s(a, b);
+}
+
+vector signed int foo2 (vector signed int a) {
+ vector signed int b = {0};
+ return vec_sld(b, b, 4);
+}
+
+/* { dg-final { scan-assembler-times {\mvsldoi\M} 1 {target le} } } */
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