[gcc r12-7111] rs6000: Fix up vspltis_shifted [PR102140]

[gcc r12-7111] rs6000: Fix up vspltis_shifted [PR102140]

[Jakub Jelinek]

https://gcc.gnu.org/g:0c3e491a4e5ae74bfbed6d167d403d262b5a4adc

commit r12-7111-g0c3e491a4e5ae74bfbed6d167d403d262b5a4adc
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Feb 8 20:14:30 2022 +0100

    rs6000: Fix up vspltis_shifted [PR102140]
    
    The following testcase ICEs, because
    (const_vector:V4SI [
                    (const_int 0 [0]) repeated x3
                    (const_int -2147483648 [0xffffffff80000000])
                ])
    is recognized as valid easy_vector_constant in between split1 pass and
    end of RA.
    The problem is that such constants need to be split, and the only
    splitter for that is:
    (define_split
      [(set (match_operand:VM 0 "altivec_register_operand")
            (match_operand:VM 1 "easy_vector_constant_vsldoi"))]
      "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
    There is only a single splitting pass before RA, so after that finishes,
    if something gets matched in between that and end of RA (after that
    can_create_pseudo_p () would be no longer true), it will never be
    successfully split and we ICE at final.cc time or earlier.
    
    The i386 backend (and a few others) already use
    (cfun->curr_properties & PROP_rtl_split_insns)
    as a test for split1 pass finished, so that some insns that should be split
    during split1 and shouldn't be matched afterwards are properly guarded.
    
    So, the following patch does that for vspltis_shifted too.
    
    2022-02-08  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/102140
            * config/rs6000/rs6000.cc (vspltis_shifted): Return false also if
            split1 pass has finished already.
    
            * gcc.dg/pr102140.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000.cc     |  7 +++++--
 gcc/testsuite/gcc.dg/pr102140.c | 23 +++++++++++++++++++++++
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index e571a0b1c96..eaba9a2d698 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -6257,8 +6257,11 @@ vspltis_shifted (rtx op)
     return false;
 
   /* We need to create pseudo registers to do the shift, so don't recognize
-     shift vector constants after reload.  */
-  if (!can_create_pseudo_p ())
+     shift vector constants after reload.  Don't match it even before RA
+     after split1 is done, because there won't be further splitting pass
+     before RA to do the splitting.  */
+  if (!can_create_pseudo_p ()
+      || (cfun->curr_properties & PROP_rtl_split_insns))
     return false;
 
   nunits = GET_MODE_NUNITS (mode);
diff --git a/gcc/testsuite/gcc.dg/pr102140.c b/gcc/testsuite/gcc.dg/pr102140.c
new file mode 100644
index 00000000000..813ba8766aa
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr102140.c
@@ -0,0 +1,23 @@
+/* PR target/102140 */
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-Og -fipa-cp -fno-tree-ccp -fno-tree-ter -Wno-psabi" } */
+
+typedef int __attribute__((__vector_size__ (64))) U;
+typedef __int128 __attribute__((__vector_size__ (64))) V;
+
+int a, b;
+
+static void
+bar (char c, V v)
+{
+  v *= c;
+  U u = a + (U) v;
+  (union { U b; }) { u };
+  b = 0;
+}
+
+void
+foo (void)
+{
+  bar (1, (V){((__int128) 9223372036854775808ULL) << 64});
+}