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* [gcc r12-7124] ICE: QImode(not SImode) operand should be passed to gen_vec_initv16qiqi in ashlv16qi3.
@ 2022-02-09 9:15 hongtao Liu
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From: hongtao Liu @ 2022-02-09 9:15 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:59b31f0e2d187ebdb3d399661e22b28e4ebd8099
commit r12-7124-g59b31f0e2d187ebdb3d399661e22b28e4ebd8099
Author: liuhongt <hongtao.liu@intel.com>
Date: Wed Feb 9 13:14:43 2022 +0800
ICE: QImode(not SImode) operand should be passed to gen_vec_initv16qiqi in ashlv16qi3.
ix86_expand_vector_init expects vals to be a parallel containing
values of individual fields which should be either element mode of the
vector mode, or a vector mode with the same element mode and smaller
number of elements.
But in the expander ashlv16qi3, the second operand is SImode which
can't be directly passed to gen_vec_initv16qiqi.
gcc/ChangeLog:
PR target/104451
* config/i386/sse.md (<insn><mode>3): lowpart_subreg
operands[2] from SImode to QImode.
gcc/testsuite/ChangeLog:
PR target/104451
* gcc.target/i386/pr104451.c: New test.
Diff:
---
gcc/config/i386/sse.md | 3 ++-
gcc/testsuite/gcc.target/i386/pr104451.c | 25 +++++++++++++++++++++++++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index d8cb7b65594..36b35f68349 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -24153,8 +24153,9 @@
negate = true;
}
par = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
+ tmp = lowpart_subreg (QImode, operands[2], SImode);
for (i = 0; i < 16; i++)
- XVECEXP (par, 0, i) = operands[2];
+ XVECEXP (par, 0, i) = tmp;
tmp = gen_reg_rtx (V16QImode);
emit_insn (gen_vec_initv16qiqi (tmp, par));
diff --git a/gcc/testsuite/gcc.target/i386/pr104451.c b/gcc/testsuite/gcc.target/i386/pr104451.c
new file mode 100644
index 00000000000..8b251ccf827
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr104451.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -mxop -O" } */
+
+typedef char __attribute__((__vector_size__ (16))) V;
+typedef unsigned char __attribute__((__vector_size__ (16))) UV;
+V v;
+UV uv;
+
+V
+foo (long c)
+{
+ return v << c;
+}
+
+V
+foo1 (long c)
+{
+ return v >> c;
+}
+
+UV
+foo2 (unsigned long uc)
+{
+ return uv >> uc;
+}
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