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* [gcc(refs/users/meissner/heads/work081)] Allow power10/power9 to inline explicit power8 functions
@ 2022-03-09 0:19 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2022-03-09 0:19 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:294119bb9e87518546578b67f1c89b4e79ba3d87
commit 294119bb9e87518546578b67f1c89b4e79ba3d87
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Mar 8 19:18:42 2022 -0500
Allow power10/power9 to inline explicit power8 functions
The power8 fusion support was set automatically when -mcpu=power8 or
-mtune=power8 was used, and it was cleared for other cpu's. However, if
you used the target attribute or target #pragma to change the default cpu
type or tuning, you would get an error that a target specifiction option
mismatch occurred.
This code moves the power8 fusion option and power8 fusion sign option
support from being option flags to being a separate option variables.
This means the code in can_inline_p will not complain about an option
mismatch. If the user did not explicitly set these options, they will be
set automatically if we are tuning for power8.
2022-03-08 Michael Meissner <meissner@linux.ibm.com>
gcc/
PR target/102059
* config/rs6000/rs6000-cpus.def (OTHER_FUSION_MASKS): Delete.
(ISA_3_0_MASKS_SERVER): Don't clear the fusion masks.
(POWERPC_MASKS): Remove OPTION_MASK_P8_FUSION.
* config/rs6000/rs6000.cc (rs6000_option_override_internal):
Change how power8 fusion options are set from being an option mask
to being separate variables.
(rs6000_opt_masks): Remove -mpower8-fusion and
-mpower8-fusion-sign.
* config/rs6000/rs6000.h (MASK_P8_FUSION): Delete.
* config/rs6000/rs6000.opt (-mpower8-fusion): Change from being an
option mask to being a separate variable.
(-mpower8-fusion-sign): Likewise.
gcc/testsuite/
PR target/102059
* gcc.target/powerpc/pr102059-4.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 22 ++++++----------
gcc/config/rs6000/rs6000.cc | 36 ++++++---------------------
gcc/config/rs6000/rs6000.h | 1 -
gcc/config/rs6000/rs6000.opt | 4 +--
gcc/testsuite/gcc.target/powerpc/pr102059-4.c | 23 +++++++++++++++++
5 files changed, 39 insertions(+), 47 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 963947f6939..ea15b8f812c 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -43,9 +43,7 @@
| OPTION_MASK_ALTIVEC \
| OPTION_MASK_VSX)
-/* For now, don't provide an embedded version of ISA 2.07. Do not set power8
- fusion here, instead set it in rs6000.cc if we are tuning for a power8
- system. */
+/* For now, don't provide an embedded version of ISA 2.07. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
@@ -54,19 +52,14 @@
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC)
-/* ISA masks setting fusion options. */
-#define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \
- | OPTION_MASK_P8_FUSION_SIGN)
-
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
-#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
- | OPTION_MASK_ISEL \
- | OPTION_MASK_MODULO \
- | OPTION_MASK_P9_MINMAX \
- | OPTION_MASK_P9_MISC \
- | OPTION_MASK_P9_VECTOR) \
- & ~OTHER_FUSION_MASKS)
+#define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \
+ | OPTION_MASK_ISEL \
+ | OPTION_MASK_MODULO \
+ | OPTION_MASK_P9_MINMAX \
+ | OPTION_MASK_P9_MISC \
+ | OPTION_MASK_P9_VECTOR) \
/* Support for the IEEE 128-bit floating point hardware requires a lot of the
VSX instructions that are part of ISA 3.0. */
@@ -140,7 +133,6 @@
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
| OPTION_MASK_NO_UPDATE \
- | OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 3afe78f5d04..cb27b1bee05 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4043,37 +4043,17 @@ rs6000_option_override_internal (bool global_init_p)
/* Enable power8 fusion if we are tuning for power8, even if we aren't
generating power8 instructions. Power9 does not optimize power8 fusion
cases. */
- if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
- {
- if (processor_target_table[tune_index].processor == PROCESSOR_POWER8)
- rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
- else
- rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
- }
-
- /* Setting additional fusion flags turns on base fusion. */
- if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN)
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
- {
- if (TARGET_P8_FUSION_SIGN)
- error ("%qs requires %qs", "-mpower8-fusion-sign",
- "-mpower8-fusion");
-
- rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
- }
- else
- rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
- }
+ if (!OPTION_SET_P (TARGET_P8_FUSION))
+ TARGET_P8_FUSION = (processor_target_table[tune_index].processor
+ == PROCESSOR_POWER8);
/* Power8 does not fuse sign extended loads with the addis. If we are
optimizing at high levels for speed, convert a sign extended load into a
zero extending load, and an explicit sign extension. */
- if (TARGET_P8_FUSION
- && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
- && optimize_function_for_speed_p (cfun)
- && optimize >= 3)
- rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
+ if (!OPTION_SET_P (TARGET_P8_FUSION_SIGN))
+ TARGET_P8_FUSION_SIGN = (TARGET_P8_FUSION
+ && optimize_function_for_speed_p (cfun)
+ && optimize >= 3);
/* ISA 3.0 vector instructions include ISA 2.07. */
if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
@@ -23983,8 +23963,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "pcrel-opt", OPTION_MASK_PCREL_OPT, false, true },
{ "popcntb", OPTION_MASK_POPCNTB, false, true },
{ "popcntd", OPTION_MASK_POPCNTD, false, true },
- { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
- { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
{ "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
{ "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 17af314416c..686d7a473e0 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -517,7 +517,6 @@ extern int rs6000_vector_align[];
#define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD
#define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW
#define MASK_FPRND OPTION_MASK_FPRND
-#define MASK_P8_FUSION OPTION_MASK_P8_FUSION
#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
#define MASK_HTM OPTION_MASK_HTM
#define MASK_ISEL OPTION_MASK_ISEL
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 4931d781c4e..3327bbb2194 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -475,11 +475,11 @@ mvsx-timode
Target RejectNegative Undocumented Ignore
mpower8-fusion
-Target Mask(P8_FUSION) Var(rs6000_isa_flags)
+Target Var(TARGET_P8_FUSION)
Fuse certain integer operations together for better performance on power8.
mpower8-fusion-sign
-Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
+Target Undocumented Var(TARGET_P8_FUSION_SIGN)
Allow sign extension in fusion operations.
mpower8-vector
diff --git a/gcc/testsuite/gcc.target/powerpc/pr102059-4.c b/gcc/testsuite/gcc.target/powerpc/pr102059-4.c
new file mode 100644
index 00000000000..5fe66f8af4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr102059-4.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+/* { dg-require-effective-target power10_ok } */
+
+/* Verify that power10 can explicity include functions compiled for power8.
+ The issue was -mcpu=power8 enables -mpower8-fusion, but -mcpu=power9 or
+ -mcpu=power10 do not set power8-fusion by default. Thus when doing this
+ compilation, they would get an error that the inline function failed in its
+ inlining due to having incompatible options. */
+
+static inline int __attribute__ ((always_inline,target("cpu=power8")))
+foo (int *b)
+{
+ *b += 10;
+ return *b;
+}
+
+int
+bar (int *a)
+{
+ *a = foo (a);
+ return 0;
+}
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