public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/meissner/heads/work081)] Improve extendditi2
@ 2022-03-12 1:00 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2022-03-12 1:00 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bf95d7129c40657e16b35e3b0309e8ea02255ff0
commit bf95d7129c40657e16b35e3b0309e8ea02255ff0
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Mar 11 20:00:05 2022 -0500
Improve extendditi2
2022-03-11 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (extendditi2): Improve code for GPR to
vector register.
Diff:
---
gcc/config/rs6000/vsx.md | 28 +++++++++++++++++++++++-----
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 7cefd9388fb..25ef1702f49 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5035,8 +5035,9 @@
;; We also need the GPR code for power9 so that we can optimize to use the
;; multiply-add instructions.
(define_insn_and_split "extendditi2"
- [(set (match_operand:TI 0 "register_operand" "=r,r,v,v,v")
- (sign_extend:TI (match_operand:DI 1 "input_operand" "r,m,b,wa,Z")))
+ [(set (match_operand:TI 0 "register_operand" "=r,r,wa,v,v")
+ (sign_extend:TI (match_operand:DI 1 "input_operand" "r,m,b, v,Z")))
+ (clobber (match_scratch:DI 2 "=&X,X,r, X,X"))
(clobber (reg:DI CA_REGNO))]
"TARGET_POWERPC64 && TARGET_MADDLD"
"#"
@@ -5046,10 +5047,27 @@
rtx dest = operands[0];
rtx src = operands[1];
int dest_regno = reg_or_subregno (dest);
+ int src_regno = ((REG_P (src) || SUBREG_P (src))
+ ? reg_or_subregno (src)
+ : -1);
+
+ /* If we are converting from a GPR to a vector register, do the sign
+ extension in a scratch GPR register, and then do the mtvsrdd. */
+ if (VSX_REGNO_P (dest_regno) && INT_REGNO_P (src_regno))
+ {
+ rtx tmp = operands[2];
+ rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno);
+ emit_insn (gen_ashrdi3 (tmp, src, GEN_INT (63)));
+ if (BYTES_BIG_ENDIAN)
+ emit_insn (gen_vsx_concat_v2di (dest_v2di, tmp, src));
+ else
+ emit_insn (gen_vsx_concat_v2di (dest_v2di, src, tmp));
+ DONE;
+ }
/* Handle conversion to GPR registers. Load up the low part and then do
a sign extension to the upper part. */
- if (INT_REGNO_P (dest_regno))
+ else if (INT_REGNO_P (dest_regno))
{
rtx dest_hi = gen_highpart (DImode, dest);
rtx dest_lo = gen_lowpart (DImode, dest);
@@ -5085,8 +5103,8 @@
gcc_unreachable ();
}
[(set_attr "length" "8")
- (set_attr "type" "shift,load,vecmove,vecperm,load")
- (set_attr "isa" "p9,p9,p10,p10,p10")])
+ (set_attr "type" "shift,load,mtvsr,vecperm,load")
+ (set_attr "isa" "p9,p9,p9,p10,p10")])
;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg
(define_insn "extendditi2_vector"
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work081)] Improve extendditi2
@ 2022-03-15 15:51 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2022-03-15 15:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:423a3cf2b30477f0099d8605984d298b7e8dd5a9
commit 423a3cf2b30477f0099d8605984d298b7e8dd5a9
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Mar 15 11:51:01 2022 -0400
Improve extendditi2
2022-03-11 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (extendditi2): Improve code for GPR to
vector register.
Diff:
---
gcc/config/rs6000/vsx.md | 28 +++++++++++++++++++++++-----
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 7cefd9388fb..25ef1702f49 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5035,8 +5035,9 @@
;; We also need the GPR code for power9 so that we can optimize to use the
;; multiply-add instructions.
(define_insn_and_split "extendditi2"
- [(set (match_operand:TI 0 "register_operand" "=r,r,v,v,v")
- (sign_extend:TI (match_operand:DI 1 "input_operand" "r,m,b,wa,Z")))
+ [(set (match_operand:TI 0 "register_operand" "=r,r,wa,v,v")
+ (sign_extend:TI (match_operand:DI 1 "input_operand" "r,m,b, v,Z")))
+ (clobber (match_scratch:DI 2 "=&X,X,r, X,X"))
(clobber (reg:DI CA_REGNO))]
"TARGET_POWERPC64 && TARGET_MADDLD"
"#"
@@ -5046,10 +5047,27 @@
rtx dest = operands[0];
rtx src = operands[1];
int dest_regno = reg_or_subregno (dest);
+ int src_regno = ((REG_P (src) || SUBREG_P (src))
+ ? reg_or_subregno (src)
+ : -1);
+
+ /* If we are converting from a GPR to a vector register, do the sign
+ extension in a scratch GPR register, and then do the mtvsrdd. */
+ if (VSX_REGNO_P (dest_regno) && INT_REGNO_P (src_regno))
+ {
+ rtx tmp = operands[2];
+ rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno);
+ emit_insn (gen_ashrdi3 (tmp, src, GEN_INT (63)));
+ if (BYTES_BIG_ENDIAN)
+ emit_insn (gen_vsx_concat_v2di (dest_v2di, tmp, src));
+ else
+ emit_insn (gen_vsx_concat_v2di (dest_v2di, src, tmp));
+ DONE;
+ }
/* Handle conversion to GPR registers. Load up the low part and then do
a sign extension to the upper part. */
- if (INT_REGNO_P (dest_regno))
+ else if (INT_REGNO_P (dest_regno))
{
rtx dest_hi = gen_highpart (DImode, dest);
rtx dest_lo = gen_lowpart (DImode, dest);
@@ -5085,8 +5103,8 @@
gcc_unreachable ();
}
[(set_attr "length" "8")
- (set_attr "type" "shift,load,vecmove,vecperm,load")
- (set_attr "isa" "p9,p9,p10,p10,p10")])
+ (set_attr "type" "shift,load,mtvsr,vecperm,load")
+ (set_attr "isa" "p9,p9,p9,p10,p10")])
;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg
(define_insn "extendditi2_vector"
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2022-03-15 15:51 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-12 1:00 [gcc(refs/users/meissner/heads/work081)] Improve extendditi2 Michael Meissner
2022-03-15 15:51 Michael Meissner
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).