[gcc(refs/users/meissner/heads/work081)] xsOptimize extendditi2 GPR to VSX register.

[gcc(refs/users/meissner/heads/work081)] xsOptimize extendditi2 GPR to VSX register.

[Michael Meissner]

https://gcc.gnu.org/g:e7173298cff3a85e5720af0300ccdd844fbf48ab

commit e7173298cff3a85e5720af0300ccdd844fbf48ab
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Mar 15 16:13:01 2022 -0400

    xsOptimize extendditi2 GPR to VSX register.
    
    2022-03-15   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * config/rs6000/vsx.md (extendditi2): Optimize extendditi2 GPR to
            VSX register.

Diff:
---
 gcc/config/rs6000/vsx.md | 82 +++++++++++++++++++++++++-----------------------
 1 file changed, 43 insertions(+), 39 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 25ef1702f49..e00643ee9e5 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5035,11 +5035,12 @@
 ;; We also need the GPR code for power9 so that we can optimize to use the
 ;; multiply-add instructions.
 (define_insn_and_split "extendditi2"
-  [(set (match_operand:TI 0 "register_operand"              "=r,r,wa,v,v")
-	(sign_extend:TI (match_operand:DI 1 "input_operand"  "r,m,b, v,Z")))
-   (clobber (match_scratch:DI 2                            "=&X,X,r, X,X"))
+  [(set (match_operand:TI 0 "register_operand" "=r, wa, v, r, v")
+	(sign_extend:TI
+	 (match_operand:DI 1 "input_operand"    "r, b,  v, m, Z")))
+   (clobber (match_scratch:DI 2                "=X, &b, X, X, X"))
    (clobber (reg:DI CA_REGNO))]
-  "TARGET_POWERPC64 && TARGET_MADDLD"
+  "TARGET_POWERPC64 && TARGET_P9_VECTOR"
   "#"
   "&& reload_completed"
   [(pc)]
@@ -5047,27 +5048,10 @@
   rtx dest = operands[0];
   rtx src = operands[1];
   int dest_regno = reg_or_subregno (dest);
-  int src_regno = ((REG_P (src) || SUBREG_P (src))
-		   ? reg_or_subregno (src)
-		   : -1);
-
-  /* If we are converting from a GPR to a vector register, do the sign
-     extension in a scratch GPR register, and then do the mtvsrdd.  */
-  if (VSX_REGNO_P (dest_regno) && INT_REGNO_P (src_regno))
-    {
-      rtx tmp = operands[2];
-      rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno);
-      emit_insn (gen_ashrdi3 (tmp, src, GEN_INT (63)));
-      if (BYTES_BIG_ENDIAN)
-	emit_insn (gen_vsx_concat_v2di (dest_v2di, tmp, src));
-      else
-	emit_insn (gen_vsx_concat_v2di (dest_v2di, src, tmp));
-      DONE;
-    }
 
   /* Handle conversion to GPR registers.  Load up the low part and then do
      a sign extension to the upper part.  */
-  else if (INT_REGNO_P (dest_regno))
+  if (INT_REGNO_P (dest_regno))
     {
       rtx dest_hi = gen_highpart (DImode, dest);
       rtx dest_lo = gen_lowpart (DImode, dest);
@@ -5075,36 +5059,56 @@
       emit_move_insn (dest_lo, src);
       /* In case src is a MEM, we have to use the destination, which is a
          register, instead of re-using the source.  */
-      rtx src2 = (REG_P (src) || SUBREG_P (src)) ? src : dest_lo;
+      rtx src2 = int_reg_operand (src, DImode) ? src : dest_lo;
       emit_insn (gen_ashrdi3 (dest_hi, src2, GEN_INT (63)));
       DONE;
     }
 
-  /* For conversion to an Altivec register, generate either a splat operation
-     or a load rightmost double word instruction.  Both instructions gets the
-     DImode value into the lower 64 bits, and then do the vextsd2q
-     instruction.  */
-
-  else if (ALTIVEC_REGNO_P (dest_regno))
+  /* For memory, use lxvrdx to load the value into the bottom of the
+     register and do the sign extension.  */
+  else if (ALTIVEC_REGNO_P (dest_regno) && MEM_P (src))
     {
-      if (MEM_P (src))
-	emit_insn (gen_vsx_lxvrdx (dest, src));
-      else
+      emit_insn (gen_vsx_lxvrdx (dest, src));
+      emit_insn (gen_extendditi2_vector (dest, dest));
+      DONE;
+    }
+
+  else
+    {  
+      int src_regno = reg_or_subregno (src);
+
+      /* If we are converting from a GPR to a vector register, do the
+         sign extension in a scratch GPR register, and then do the
+         mtvsrdd.  */
+      if (VSX_REGNO_P (dest_regno) && INT_REGNO_P (src_regno))
+	{
+	  rtx tmp = operands[2];
+	  rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno);
+	  emit_insn (gen_ashrdi3 (tmp, src, GEN_INT (63)));
+	  if (BYTES_BIG_ENDIAN)
+	    emit_insn (gen_vsx_concat_v2di (dest_v2di, tmp, src));
+	  else
+	    emit_insn (gen_vsx_concat_v2di (dest_v2di, src, tmp));
+	  DONE;
+	}
+
+     /* For conversion to an Altivec register, generate a splat operation to
+         to get the value in the bottom 64-bits.  */
+      else if (ALTIVEC_REGNO_P (dest_regno) && ALTIVEC_REGNO_P (src_regno))
 	{
 	  rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno);
 	  emit_insn (gen_vsx_splat_v2di (dest_v2di, src));
+	  emit_insn (gen_extendditi2_vector (dest, dest));
+	  DONE;
 	}
 
-      emit_insn (gen_extendditi2_vector (dest, dest));
-      DONE;
+      else
+	gcc_unreachable ();
     }
-
-  else
-    gcc_unreachable ();
 }
   [(set_attr "length" "8")
-   (set_attr "type" "shift,load,mtvsr,vecperm,load")
-   (set_attr "isa" "p9,p9,p9,p10,p10")])
+   (set_attr "type" "shift,mtvsr,vecperm,load,vecload")
+   (set_attr "isa"  "*,    *,    p10,    *,   p10")])
 
 ;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg
 (define_insn "extendditi2_vector"