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* [gcc r12-7731] RISC-V: Implement misc macro for vector extensions.
@ 2022-03-21 8:29 Kito Cheng
0 siblings, 0 replies; only message in thread
From: Kito Cheng @ 2022-03-21 8:29 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5177634148aab7a7b193eaa9b8c73ce00a38c481
commit r12-7731-g5177634148aab7a7b193eaa9b8c73ce00a38c481
Author: Kito Cheng <kito.cheng@sifive.com>
Date: Mon Mar 21 16:16:14 2022 +0800
RISC-V: Implement misc macro for vector extensions.
See also:
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
Update flag name and mask name.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Define
misc macro for vector extensions.
* config/riscv/riscv-opts.h (MASK_VECTOR_EEW_32): Rename to ...
(MASK_VECTOR_ELEN_32): ... this.
(MASK_VECTOR_EEW_64): Rename to ...
(MASK_VECTOR_ELEN_64): ... this.
(MASK_VECTOR_EEW_FP_32): Rename to ...
(MASK_VECTOR_ELEN_FP_32): ... this.
(MASK_VECTOR_EEW_FP_64): Rename to ...
(MASK_VECTOR_ELEN_FP_64): ... this.
(TARGET_VECTOR_ELEN_32): New.
(TARGET_VECTOR_ELEN_64): Ditto.
(TARGET_VECTOR_ELEN_FP_32): Ditto.
(TARGET_VECTOR_ELEN_FP_64): Ditto.
(TARGET_MIN_VLEN): Ditto.
* config/riscv/riscv.opt (riscv_vector_eew_flags): Rename to ...
(riscv_vector_elen_flags): ... this.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-13.c: New.
* gcc.target/riscv/arch-14.c: Ditto.
* gcc.target/riscv/arch-15.c: Ditto.
* gcc.target/riscv/predef-18.c: Ditto.
* gcc.target/riscv/predef-19.c: Ditto.
* gcc.target/riscv/predef-20.c: Ditto.
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 16 +++---
gcc/config/riscv/riscv-c.cc | 18 ++++++
gcc/config/riscv/riscv-opts.h | 25 +++++++--
gcc/config/riscv/riscv.opt | 2 +-
gcc/testsuite/gcc.target/riscv/arch-13.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-14.c | 5 ++
gcc/testsuite/gcc.target/riscv/arch-15.c | 5 ++
gcc/testsuite/gcc.target/riscv/predef-18.c | 84 ++++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/predef-19.c | 88 ++++++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/predef-20.c | 84 ++++++++++++++++++++++++++++
10 files changed, 319 insertions(+), 13 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 48c4fabdc6b..1501242e296 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1116,16 +1116,16 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zve64f", &gcc_options::x_target_flags, MASK_VECTOR},
{"zve64d", &gcc_options::x_target_flags, MASK_VECTOR},
- /* We don't need to put complete EEW/EEW_FP info here, due to the
+ /* We don't need to put complete ELEN/ELEN_FP info here, due to the
implication relation of vector extension.
- e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_EEW_FP_64,
- MASK_VECTOR_EEW_FP_32, MASK_VECTOR_EEW_64 and MASK_VECTOR_EEW_32
+ e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_ELEN_FP_64,
+ MASK_VECTOR_ELEN_FP_32, MASK_VECTOR_ELEN_64 and MASK_VECTOR_ELEN_32
due to the extension implication. */
- {"zve32x", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_32},
- {"zve32f", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32},
- {"zve64x", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_64},
- {"zve64f", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32},
- {"zve64d", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_64},
+ {"zve32x", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32},
+ {"zve32f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32},
+ {"zve64x", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
+ {"zve64f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32},
+ {"zve64d", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64},
{"zvl32b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B},
{"zvl64b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B},
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 73c62f41274..eb7ef09297e 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -104,6 +104,24 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
}
+ if (TARGET_MIN_VLEN != 0)
+ builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN);
+
+ if (TARGET_VECTOR_ELEN_64)
+ builtin_define_with_int_value ("__riscv_v_elen", 64);
+ else if (TARGET_VECTOR_ELEN_32)
+ builtin_define_with_int_value ("__riscv_v_elen", 32);
+
+ if (TARGET_VECTOR_ELEN_FP_64)
+ builtin_define_with_int_value ("__riscv_v_elen_fp", 64);
+ else if (TARGET_VECTOR_ELEN_FP_32)
+ builtin_define_with_int_value ("__riscv_v_elen_fp", 32);
+ else if (TARGET_MIN_VLEN != 0)
+ builtin_define_with_int_value ("__riscv_v_elen_fp", 0);
+
+ if (TARGET_MIN_VLEN)
+ builtin_define ("__riscv_vector");
+
/* Define architecture extension test macros. */
builtin_define_with_int_value ("__riscv_arch_test", 1);
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 929e4e3a7c5..15bb5e76854 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -105,10 +105,19 @@ enum stack_protector_guard {
#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
-#define MASK_VECTOR_EEW_32 (1 << 0)
-#define MASK_VECTOR_EEW_64 (1 << 1)
-#define MASK_VECTOR_EEW_FP_32 (1 << 2)
-#define MASK_VECTOR_EEW_FP_64 (1 << 3)
+#define MASK_VECTOR_ELEN_32 (1 << 0)
+#define MASK_VECTOR_ELEN_64 (1 << 1)
+#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
+#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
+
+#define TARGET_VECTOR_ELEN_32 \
+ ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
+#define TARGET_VECTOR_ELEN_64 \
+ ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
+#define TARGET_VECTOR_ELEN_FP_32 \
+ ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
+#define TARGET_VECTOR_ELEN_FP_64 \
+ ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
#define MASK_ZVL32B (1 << 0)
#define MASK_ZVL64B (1 << 1)
@@ -136,4 +145,12 @@ enum stack_protector_guard {
#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
+/* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
+ set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
+ popcount to caclulate the minimal VLEN. */
+#define TARGET_MIN_VLEN \
+ ((riscv_zvl_flags == 0) \
+ ? 0 \
+ : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
+
#endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 9fffc08220d..492aad12324 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -204,7 +204,7 @@ TargetVariable
int riscv_zk_subext
TargetVariable
-int riscv_vector_eew_flags
+int riscv_vector_elen_flags
TargetVariable
int riscv_zvl_flags
diff --git a/gcc/testsuite/gcc.target/riscv/arch-13.c b/gcc/testsuite/gcc.target/riscv/arch-13.c
new file mode 100644
index 00000000000..59a1a03d790
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-13.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gcv -mabi=ilp32 -mcmodel=medlow" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-14.c b/gcc/testsuite/gcc.target/riscv/arch-14.c
new file mode 100644
index 00000000000..8a911a67dee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-14.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zve64f_zvl128b -mabi=ilp32 -mcmodel=medlow" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-15.c b/gcc/testsuite/gcc.target/riscv/arch-15.c
new file mode 100644
index 00000000000..dc494476dcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-15.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gcv_zvl128b -mabi=ilp32 -mcmodel=medlow" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-18.c b/gcc/testsuite/gcc.target/riscv/predef-18.c
new file mode 100644
index 00000000000..0f53b41cede
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-18.c
@@ -0,0 +1,84 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gcv -mabi=lp64d -mcmodel=medlow -misa-spec=2.2" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if !defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if !defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if !defined(__riscv_zvl128b)
+#error "__riscv_zvl128b"
+#endif
+
+#if !defined(__riscv_zvl64b)
+#error "__riscv_zvl64b"
+#endif
+
+#if !defined(__riscv_zvl32b)
+#error "__riscv_zvl32b"
+#endif
+
+#if !defined(__riscv_vector)
+#error "__riscv_vector"
+#endif
+
+#if !defined(__riscv_v_min_vlen)
+#error "__riscv_v_min_vlen"
+#if __riscv_v_min_vlen != 128
+#error "__riscv_v_elen != 128"
+#endif
+#endif
+
+#if !defined(__riscv_v_elen)
+#error "__riscv_v_elen"
+#if __riscv_v_elen != 64
+#error "__riscv_v_elen != 64"
+#endif
+#endif
+
+#if !defined(__riscv_v_elen_fp)
+#error "__riscv_v_elen_fp"
+#if __riscv_v_elen_fp != 64
+#error "__riscv_v_elen_fp != 64"
+#endif
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c b/gcc/testsuite/gcc.target/riscv/predef-19.c
new file mode 100644
index 00000000000..2b90702192b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-19.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zve32x -mabi=lp64d -mcmodel=medlow -misa-spec=2.2" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if !defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if defined(__riscv_zvl128b)
+#error "__riscv_zvl128b"
+#endif
+
+#if defined(__riscv_zvl64b)
+#error "__riscv_zvl64b"
+#endif
+
+#if !defined(__riscv_zvl32b)
+#error "__riscv_zvl32b"
+#endif
+
+#if !defined(__riscv_zve32x)
+#error "__riscv_zve32x"
+#endif
+
+#if !defined(__riscv_vector)
+#error "__riscv_vector"
+#endif
+
+#if !defined(__riscv_v_min_vlen)
+#error "__riscv_v_min_vlen"
+#if __riscv_v_min_vlen != 32
+#error "__riscv_v_elen != 32"
+#endif
+#endif
+
+#if !defined(__riscv_v_elen)
+#error "__riscv_v_elen"
+#if __riscv_v_elen != 32
+#error "__riscv_v_elen != 32"
+#endif
+#endif
+
+#if !defined(__riscv_v_elen_fp)
+#error "__riscv_v_elen_fp"
+#if __riscv_v_elen_fp != 0
+#error "__riscv_v_elen_fp != 0"
+#endif
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-20.c b/gcc/testsuite/gcc.target/riscv/predef-20.c
new file mode 100644
index 00000000000..927d25ffc41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-20.c
@@ -0,0 +1,84 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gcv_zvl512b -mabi=lp64d -mcmodel=medlow -misa-spec=2.2" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+#if !defined(__riscv_m)
+#error "__riscv_m"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if !defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if !defined(__riscv_zvl128b)
+#error "__riscv_zvl128b"
+#endif
+
+#if !defined(__riscv_zvl64b)
+#error "__riscv_zvl64b"
+#endif
+
+#if !defined(__riscv_zvl32b)
+#error "__riscv_zvl32b"
+#endif
+
+#if !defined(__riscv_vector)
+#error "__riscv_vector"
+#endif
+
+#if !defined(__riscv_v_min_vlen)
+#error "__riscv_v_min_vlen"
+#if __riscv_v_min_vlen != 512
+#error "__riscv_v_elen != 512"
+#endif
+#endif
+
+#if !defined(__riscv_v_elen)
+#error "__riscv_v_elen"
+#if __riscv_v_elen != 64
+#error "__riscv_v_elen != 64"
+#endif
+#endif
+
+#if !defined(__riscv_v_elen_fp)
+#error "__riscv_v_elen_fp"
+#if __riscv_v_elen_fp != 64
+#error "__riscv_v_elen_fp != 64"
+#endif
+#endif
+
+ return 0;
+}
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