[gcc(refs/users/meissner/heads/work083)] Revert patches.

[gcc(refs/users/meissner/heads/work083)] Revert patches.

[Michael Meissner]

https://gcc.gnu.org/g:05ee3669b7e5606cd8fc2952f34fe69d25083fc3

commit 05ee3669b7e5606cd8fc2952f34fe69d25083fc3
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 24 17:28:05 2022 -0400

    Revert patches.
    
    2022-03-24   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            PR target/99392
            Revert patch.
            * config/rs6000/rs6000.md (vsx_extract_<mode>): Allow destination
            to be an Altivec register.
    
    2022-03-24   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            PR target/99392
            Revert patch.
            * config/rs6000/rs6000.md (vsx_extract_<mode>): Use the correct
            insn type for the alternatives.

Diff:
---
 gcc/config/rs6000/vsx.md | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 844cca7c369..ad722cff70f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3397,12 +3397,15 @@
 ;; Optimize cases were we can do a simple or direct move.
 ;; Or see if we can avoid doing the move at all
 
+;; There are some unresolved problems with reload that show up if an Altivec
+;; register was picked.  Limit the scalar value to FPRs for now.
+
 (define_insn "vsx_extract_<mode>"
-  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=wa, wa, wr, wr")
+  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=d, d,  wr, wr")
 	(vec_select:<VS_scalar>
-	 (match_operand:VSX_D 1 "gpc_reg_operand"       "wa, wa, wa, wa")
+	 (match_operand:VSX_D 1 "gpc_reg_operand"      "wa, wa, wa, wa")
 	 (parallel
-	  [(match_operand:QI 2 "const_0_to_1_operand"   "wD, n,  wD, n")])))]
+	  [(match_operand:QI 2 "const_0_to_1_operand"  "wD, n,  wD, n")])))]
   "VECTOR_MEM_VSX_P (<MODE>mode)"
 {
   int element = INTVAL (operands[2]);
@@ -3448,7 +3451,7 @@
   else
     gcc_unreachable ();
 }
-  [(set_attr "type" "vecsimple,vecperm,mfvsr,mfvsr")
+  [(set_attr "type" "veclogical,mfvsr,mfvsr,vecperm")
    (set_attr "isa" "*,*,p8v,p9v")])
 
 ;; Optimize extracting a single scalar element from memory.