[gcc(refs/users/meissner/heads/work084)] Revert patch.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:e13ad3cdd6655382e05105b8e3b47ce4aa0be70d

commit e13ad3cdd6655382e05105b8e3b47ce4aa0be70d
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 1 20:03:00 2022 -0400

    Revert patch.
    
    2022-04-01   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            Revert patch.
            * config/rs6000/vsx.md (vsx_lxvr<wd>x): Add support for loading to
            GPR registers.
            (vsx_stxvr<wd>x): Add support for storing from GPR registers.
            (zero_extendditi2): New insn.
    
    gcc/testsuite/
            Revert patch.
            * gcc.target/powerpc/zero-extend-di-ti.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 103 +++------------------
 .../gcc.target/powerpc/zero-extend-di-ti.c         |  62 -------------
 2 files changed, 15 insertions(+), 150 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 27810287ad7..c091e5e2f47 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1315,48 +1315,23 @@
     }
 })
 
-;; Load rightmost element from load_data using lxvrbx, lxvrhx, lxvrwx, lxvrdx.
-;; Support TImode being in a GPR register to prevent generating lvxr{d,w,b}x
-;; and then two direct moves if we ultimately need the value in a GPR register.
-(define_insn_and_split "vsx_lxvr<wd>x"
-  [(set (match_operand:TI 0 "register_operand" "=r,wa")
-	(zero_extend:TI (match_operand:INT_ISA3  1 "memory_operand" "m,Z")))]
-  "TARGET_POWERPC64 && TARGET_POWER10"
-  "@
-   #
-   lxvr<wd>x %x0,%y1"
-  "&& reload_completed && int_reg_operand (operands[0], TImode)"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (const_int 0))]
-{
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-
-  operands[2] = gen_lowpart (DImode, op0);
-  operands[3] = (<MODE>mode == DImode
-		 ? op1
-		 : gen_rtx_ZERO_EXTEND (DImode, op1));
-
-  operands[4] = gen_highpart (DImode, op0);
-}
-  [(set_attr "type" "load,vecload")
-   (set_attr "num_insns" "2,*")])
+;; Load rightmost element from load_data
+;; using lxvrbx, lxvrhx, lxvrwx, lxvrdx.
+(define_insn "vsx_lxvr<wd>x"
+  [(set (match_operand:TI 0 "vsx_register_operand" "=wa")
+	(zero_extend:TI (match_operand:INT_ISA3  1 "memory_operand" "Z")))]
+  "TARGET_POWER10"
+  "lxvr<wd>x %x0,%y1"
+  [(set_attr "type" "vecload")])
 
-;; Store rightmost element into store_data using stxvrbx, stxvrhx, strvxwx,
-;; strvxdx.  Support TImode being in a GPR register to prevent generating
-;; mtvsrdd and then stvxr{d,w,b}x instead of a GPR store.
+;; Store rightmost element into store_data
+;; using stxvrbx, stxvrhx, strvxwx, strvxdx.
 (define_insn "vsx_stxvr<wd>x"
-  [(set (match_operand:INT_ISA3 0 "memory_operand" "=m,Z")
-	(truncate:INT_ISA3 (match_operand:TI 1 "register_operand" "r,wa")))]
-  "TARGET_POWERPC64 && TARGET_POWER10"
-{
-  if (vsx_register_operand (operands[1], TImode))
-    return "stxvr<wc>x %x1,%y0";
-
-  operands[2] = gen_lowpart (<MODE>mode, operands[1]);
-  return "st<wd>%U0%X0 %2,%0";
-}
-  [(set_attr "type" "store,vecstore")])
+  [(set (match_operand:INT_ISA3 0 "memory_operand" "=Z")
+	(truncate:INT_ISA3 (match_operand:TI 1 "vsx_register_operand" "wa")))]
+  "TARGET_POWER10"
+  "stxvr<wd>x %x1,%y0"
+  [(set_attr "type" "vecstore")])
 
 ;; Explicit load/store expanders for the builtin functions for lxvd2x, etc.,
 ;; when you really want their element-reversing behavior.
@@ -5044,54 +5019,6 @@
   DONE;
 })
 
-;; Zero extend DI to TI.  If we don't have the MTVSRDD instruction (and LXVRDX
-;; in the case of power10), we use the machine independent code.  If we are
-;; loading up GPRs, we fall back to the old code.
-(define_insn_and_split "zero_extendditi2"
-  [(set (match_operand:TI 0 "register_operand"                 "=r,r, wa,&wa")
-	(zero_extend:TI (match_operand:DI 1 "register_operand"  "r,wa,r,  wa")))]
-  "TARGET_POWERPC64 && TARGET_P9_VECTOR"
-  "@
-   #
-   #
-   mtvsrdd %x0,0,%1
-   #"
-  "&& reload_completed
-   && (int_reg_operand (operands[0], TImode)
-       || vsx_register_operand (operands[1], DImode))"
-  [(pc)]
-{
-  rtx dest = operands[0];
-  rtx src = operands[1];
-  int dest_regno = reg_or_subregno (dest);
-
-  /* Handle conversion to GPR registers.  Load up the low part and then do
-     zero out the upper part.  */
-  if (INT_REGNO_P (dest_regno))
-    {
-      rtx dest_hi = gen_highpart (DImode, dest);
-      rtx dest_lo = gen_lowpart (DImode, dest);
-
-      emit_move_insn (dest_lo, src);
-      emit_move_insn (dest_hi, const0_rtx);
-      DONE;
-    }
-
-  /* For settomg a VSX register from another VSX register, clear the result
-     register, and use XXPERMDI to shift the value into the lower 64-bits.  */
-  rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno);
-  rtx dest_di = gen_rtx_REG (DImode, dest_regno);
-
-  emit_move_insn (dest_v2di, CONST0_RTX (V2DImode));
-  if (BYTES_BIG_ENDIAN)
-    emit_insn (gen_vsx_concat_v2di (dest_v2di, dest_di, src));
-  else
-    emit_insn (gen_vsx_concat_v2di (dest_v2di, src, dest_di));
-  DONE;
-}
-  [(set_attr "type"   "integer,mfvsr,vecmove,vecperm")
-   (set_attr "length" "8,      8,    *,      8")])
-
 ;; Sign extend DI to TI.  We provide both GPR targets and Altivec targets on
 ;; power10.  On earlier systems, the machine independent code will generate a
 ;; shift left to sign extend the 64-bit value to 128-bit.
diff --git a/gcc/testsuite/gcc.target/powerpc/zero-extend-di-ti.c b/gcc/testsuite/gcc.target/powerpc/zero-extend-di-ti.c
deleted file mode 100644
index ab5f5d89d4d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/zero-extend-di-ti.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-require-effective-target int128     } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* This patch makes sure the various optimization and code paths are done for
-   zero extending DImode to TImode on power10.  */
-
-__uint128_t
-gpr_to_gpr (unsigned long long a)
-{
-  /* li 4,0.  */
-  return a;
-}
-
-__uint128_t
-mem_to_gpr (unsigned long long *p)
-{
-  /* ld 3,0(3); li 4,0.  */
-  return *p;
-}
-
-__uint128_t
-vsx_to_gpr (__uint128_t *p, double d)
-{
-  /* fctiduz 1,1; li 4,0;mfvsrd 3,1.  */
-  return (unsigned long long)d;
-}
-
-void
-gpr_to_vsx (__uint128_t *p, unsigned long long a)
-{
-  /* mtvsrdd 0,0,4; stxv 0,0(3).  */
-  __uint128_t b = a;
-  __asm__ (" # %x0" : "+wa" (b));
-  *p = b;
-}
-
-void
-mem_to_vsx (__uint128_t *p, unsigned long long *q)
-{
-  /* lxvrdx 0,0,4; stxv 0,0(3).  */
-  __uint128_t a = *q;
-  __asm__ (" # %x0" : "+wa" (a));
-  *p = a;
-}
-
-void
-vsx_to_vsx (__uint128_t *p, double d)
-{
-  /* fctiduz 1,1; xxspltib 0,0; xxpermdi 0,0,1,0; stxv 0,0(3).  */
-  __uint128_t a = (unsigned long long)d;
-  __asm__ (" # %x0" : "+wa" (a));
-  *p = a;
-}
-
-/* { dg-final { scan-assembler-times {\mli\M}       3 } } */
-/* { dg-final { scan-assembler-times {\mld\M}       1 } } */
-/* { dg-final { scan-assembler-times {\mlxvrdx\M}   3 } } */
-/* { dg-final { scan-assembler-times {\mmfvsrd\M}   1 } } */
-/* { dg-final { scan-assembler-times {\mmtvsrdd\M}  1 } } */
-/* { dg-final { scan-assembler-times {\mstxv\M}     1 } } */
-/* { dg-final { scan-assembler-times {\mxxpermdi\M} 1 } } */