[gcc(refs/vendors/ARM/heads/morello)] aarch64: Callee-saved registers are part-clobbered on hybrid

[gcc(refs/vendors/ARM/heads/morello)] aarch64: Callee-saved registers are part-clobbered on hybrid

[Matthew Malcomson]

https://gcc.gnu.org/g:39ad9561dc3e6d4a829ca9c31b549f62622cfb23

commit 39ad9561dc3e6d4a829ca9c31b549f62622cfb23
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Mon Apr 11 17:33:13 2022 +0100

    aarch64: Callee-saved registers are part-clobbered on hybrid
    
    On hybrid Morello, the PCS only requires the x-registers to be
    callee-saved. The upper bits in the callee-saved c-registers can
    therefore be clobbered by function calls. GCC wasn't aware of this, so
    it would incorrectly allocate a callee-saved register for the execution
    test added with this patch.
    
    Incidentally, the execution test added with the patch shows a couple of
    issues with the builtin patterns: the constraints on the two comparison
    builtins were wrong.
    
    This patch fixes both of these issues.
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64-morello.md (aarch64_cap_bit_equality):
            Drop bogus output modifier from source operand constraints.
            (aarch64_cap_subset_of): Likewise.
            * config/aarch64/aarch64.c
            (aarch64_hard_regno_call_part_clobbered): Return true for
            CADImode registers on hybrid.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/aarch64/morello/callee-saves.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-morello.md                   |  4 ++--
 gcc/config/aarch64/aarch64.c                            |  3 +++
 gcc/testsuite/gcc.target/aarch64/morello/callee-saves.c | 16 ++++++++++++++++
 3 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-morello.md b/gcc/config/aarch64/aarch64-morello.md
index e594d6d7f1d..e41ca8e8644 100644
--- a/gcc/config/aarch64/aarch64-morello.md
+++ b/gcc/config/aarch64/aarch64-morello.md
@@ -353,7 +353,7 @@
 
 (define_insn "aarch64_cap_bit_equality"
   [(set (reg:CC_Z CC_REGNUM)
-        (unspec:CC_Z [(match_operand:CADI 0 "register_operand" "=rk")
+        (unspec:CC_Z [(match_operand:CADI 0 "register_operand" "rk")
                     (match_operand:CADI 1 "register_operand" "r")]
           UNSPEC_CHERI_BIT_EQ)
         )]
@@ -432,7 +432,7 @@
 
 (define_insn "aarch64_cap_subset_of"
   [(set (reg:CC_N CC_REGNUM)
-        (unspec:CC_N [(match_operand:CADI 0 "register_operand" "=rk")
+        (unspec:CC_N [(match_operand:CADI 0 "register_operand" "rk")
                     (match_operand:CADI 1 "register_operand" "rk")]
           UNSPEC_CHERI_SUBSET_TEST)
         )]
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 7fbc1970417..9b1e0d71dd1 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2868,6 +2868,9 @@ aarch64_hard_regno_call_part_clobbered (unsigned int abi_id,
 					unsigned int regno,
 					machine_mode mode)
 {
+  if (TARGET_CAPABILITY_HYBRID && mode == CADImode && GP_REGNUM_P (regno))
+    return true;
+
   if (FP_REGNUM_P (regno) && abi_id != ARM_PCS_SVE)
     {
       poly_int64 per_register_size = GET_MODE_SIZE (mode);
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/callee-saves.c b/gcc/testsuite/gcc.target/aarch64/morello/callee-saves.c
new file mode 100644
index 00000000000..5eaf34f33e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/morello/callee-saves.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-skip-if "" { *-*-* } { "-mfake-capability" } { "" } }  */
+
+__attribute ((noipa))
+void * __capability foo (void * __capability t)
+{
+  asm("mov x20, #0" ::: "x20");
+  return t;
+}
+
+int main(void)
+{
+  void * __capability c = __builtin_cheri_global_data_get ();
+  if (!__builtin_cheri_equal_exact (c, foo (c)))
+    __builtin_abort ();
+}