[gcc(refs/vendors/ARM/heads/morello)] aarch64: Rework vector split code

[gcc(refs/vendors/ARM/heads/morello)] aarch64: Rework vector split code

[Matthew Malcomson]

https://gcc.gnu.org/g:67417a0967f872d1d930f6bdf05276f657f16391

commit 67417a0967f872d1d930f6bdf05276f657f16391
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Fri Apr 8 16:53:56 2022 +0100

    aarch64: Rework vector split code
    
    We have three sets of 128-bit splitters: one for TI, one for TF
    and one for vector modes.  The TI and TF code already shared
    the same underlying routines, but the vector code had separate
    (but essentially equivalent) code.  This patch makes them all
    use a single define_split.

Diff:
---
 gcc/config/aarch64/aarch64-protos.h |  2 --
 gcc/config/aarch64/aarch64-simd.md  | 56 -------------------------------------
 gcc/config/aarch64/aarch64.c        | 22 +++------------
 gcc/config/aarch64/aarch64.md       | 17 ++---------
 gcc/config/aarch64/predicates.md    |  5 ++--
 5 files changed, 10 insertions(+), 92 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index 1a6588826fa..954ffa45ad1 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -665,8 +665,6 @@ bool aarch64_mov128_immediate (rtx);
 
 void aarch64_split_simd_combine (rtx, rtx, rtx);
 
-void aarch64_split_simd_move (rtx, rtx);
-
 /* Check for a legitimate floating point constant for FMOV.  */
 bool aarch64_float_const_representable_p (rtx);
 
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 37adee676fd..47f84773d9e 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -179,62 +179,6 @@
   [(set_attr "type" "neon_store1_1reg<q>")]
 )
 
-(define_split
-  [(set (match_operand:VQMOV 0 "register_operand" "")
-      (match_operand:VQMOV 1 "register_operand" ""))]
-  "TARGET_SIMD && reload_completed
-   && GP_REGNUM_P (REGNO (operands[0]))
-   && GP_REGNUM_P (REGNO (operands[1]))"
-  [(const_int 0)]
-{
-  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
-  DONE;
-})
-
-(define_split
-  [(set (match_operand:VQMOV 0 "register_operand" "")
-        (match_operand:VQMOV 1 "register_operand" ""))]
-  "TARGET_SIMD && reload_completed
-   && ((FP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1])))
-       || (GP_REGNUM_P (REGNO (operands[0])) && FP_REGNUM_P (REGNO (operands[1]))))"
-  [(const_int 0)]
-{
-  aarch64_split_simd_move (operands[0], operands[1]);
-  DONE;
-})
-
-(define_expand "@aarch64_split_simd_mov<mode>"
-  [(set (match_operand:VQMOV 0)
-        (match_operand:VQMOV 1))]
-  "TARGET_SIMD"
-  {
-    rtx dst = operands[0];
-    rtx src = operands[1];
-
-    if (GP_REGNUM_P (REGNO (src)))
-      {
-        rtx src_low_part = gen_lowpart (<VHALF>mode, src);
-        rtx src_high_part = gen_highpart (<VHALF>mode, src);
-
-        emit_insn
-          (gen_move_lo_quad_<mode> (dst, src_low_part));
-        emit_insn
-          (gen_move_hi_quad_<mode> (dst, src_high_part));
-      }
-
-    else
-      {
-        rtx dst_low_part = gen_lowpart (<VHALF>mode, dst);
-        rtx dst_high_part = gen_highpart (<VHALF>mode, dst);
-	rtx lo = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
-	rtx hi = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
-        emit_insn (gen_aarch64_get_half<mode> (dst_low_part, src, lo));
-        emit_insn (gen_aarch64_get_half<mode> (dst_high_part, src, hi));
-      }
-    DONE;
-  }
-)
-
 (define_expand "aarch64_get_half<mode>"
   [(set (match_operand:<VHALF> 0 "register_operand")
         (vec_select:<VHALF>
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index cab081fc1d0..8d268af60eb 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3659,7 +3659,7 @@ aarch64_split_128bit_move (rtx dst, rtx src)
 
   machine_mode mode = GET_MODE (dst);
 
-  gcc_assert (mode == TImode || mode == TFmode);
+  gcc_assert (known_eq (GET_MODE_SIZE (mode), 16));
   gcc_assert (!(side_effects_p (src) || side_effects_p (dst)));
   gcc_assert (mode == GET_MODE (src) || GET_MODE (src) == VOIDmode);
 
@@ -3755,23 +3755,6 @@ aarch64_split_simd_combine (rtx dst, rtx src1, rtx src2)
   return;
 }
 
-/* Split a complex SIMD move.  */
-
-void
-aarch64_split_simd_move (rtx dst, rtx src)
-{
-  machine_mode src_mode = GET_MODE (src);
-  machine_mode dst_mode = GET_MODE (dst);
-
-  gcc_assert (VECTOR_MODE_P (dst_mode));
-
-  if (REG_P (dst) && REG_P (src))
-    {
-      gcc_assert (VECTOR_MODE_P (src_mode));
-      emit_insn (gen_aarch64_split_simd_mov (src_mode, dst, src));
-    }
-}
-
 bool
 aarch64_zero_extend_const_eq (machine_mode xmode, rtx x,
 			      machine_mode ymode, rtx y)
@@ -19236,6 +19219,9 @@ aarch64_mov_operand_p (rtx x, machine_mode mode)
   if (CONST_NULL_P (x))
     return true;
 
+  if (CONST_DOUBLE_P (x))
+    return aarch64_float_const_zero_rtx_p (x);
+
   if (VECTOR_MODE_P (GET_MODE (x)))
     {
       /* Require predicate constants to be VNx16BI before RA, so that we
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 759b0fec974..06f596bc3e7 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1417,11 +1417,11 @@
    (set_attr "arch" "*,*,*,simd,*,*,*,*,*,fp,fp")]
 )
 
-;; Split a TImode GPR move into its component DImode pieces, taking
+;; Split a 128-bit GPR move into its component DImode pieces, taking
 ;; care to handle overlapping source and dest registers.
 (define_split
-   [(set (match_operand:TI 0 "nonimmediate_operand" "")
-	 (match_operand:TI 1 "aarch64_mov_operand" ""))]
+   [(set (match_operand:ANY_Q 0 "nonimmediate_operand" "")
+	 (match_operand:ANY_Q 1 "aarch64_mov_operand" ""))]
   "reload_completed && aarch64_split_128bit_move_p (operands[0], operands[1])"
   [(const_int 0)]
 {
@@ -1571,17 +1571,6 @@
    (set_attr "arch" "simd,*,*,*,simd,*,*,*,*,*,*,*,*,*")]
 )
 
-(define_split
-   [(set (match_operand:TF 0 "nonimmediate_operand" "")
-	 (match_operand:TF 1 "general_operand" ""))]
-  "reload_completed && aarch64_split_128bit_move_p (operands[0], operands[1])"
-  [(const_int 0)]
-  {
-    aarch64_split_128bit_move (operands[0], operands[1]);
-    DONE;
-  }
-)
-
 ;; 0 is dst
 ;; 1 is src
 ;; 2 is size of copy in bytes
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index ceca71dc292..97a405c0297 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -338,14 +338,15 @@
 
 (define_predicate "aarch64_mov_operand"
   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high,
-		    const_poly_int,const_vector,const_null,const_wide_int")
+		    const_poly_int,const_vector,const_null,const_wide_int,
+		    const_double")
        (ior (match_operand 0 "register_operand")
 	    (ior (match_operand 0 "memory_operand")
 		 (match_test "aarch64_mov_operand_p (op, mode)")))))
 
 (define_predicate "aarch64_nonmemory_operand"
   (and (match_code "reg,subreg,const,const_int,symbol_ref,label_ref,high,
-		    const_poly_int,const_vector,const_wide_int")
+		    const_poly_int,const_vector,const_wide_int,const_double")
        (ior (match_operand 0 "register_operand")
 	    (match_test "aarch64_mov_operand_p (op, mode)"))))