[gcc(refs/vendors/ARM/heads/morello)] morello: Add C machine constraint as an alias of r

[gcc(refs/vendors/ARM/heads/morello)] morello: Add C machine constraint as an alias of r

[Matthew Malcomson]

https://gcc.gnu.org/g:2b0f5e04449b1b0dc577ef1e822b661777ac569d

commit 2b0f5e04449b1b0dc577ef1e822b661777ac569d
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Fri Apr 29 10:59:10 2022 +0100

    morello: Add C machine constraint as an alias of r
    
    This adds C as a machine constraint with `GENERAL_REGS` as the
    condition.  This matches the r constraint in common.md. The C
    constraint is not meant to be used in patterns, only to enable
    the compilation of CHERI-specific inline assembly.

Diff:
---
 gcc/config/aarch64/constraints.md                       |  5 +++++
 gcc/doc/md.texi                                         |  7 +++++++
 gcc/testsuite/gcc.target/aarch64/morello/c-constraint.c | 16 ++++++++++++++++
 3 files changed, 28 insertions(+)

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index c80a5fed2db..bfa379b2fe9 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -48,6 +48,11 @@
 (define_register_constraint "y" "FP_LO8_REGS"
   "Floating point and SIMD vector registers V0 - V7.")
 
+(define_register_constraint "C" "GENERAL_REGS"
+  "An alias of the r constraint for Morello capability registers.  This is not
+   intended to ever be used in backend patterns.  It only exists to enable the
+   compiling of CHERI-specific inline asm")
+
 (define_constraint "c"
  "@internal The condition code register."
   (match_operand 0 "cc_register"))
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 062d8c700be..63eaff17864 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -1760,6 +1760,13 @@ One of the low eight SVE predicate registers (@code{P0} to @code{P7})
 @item Upa
 Any of the SVE predicate registers (@code{P0} to @code{P15})
 
+@item C
+An alias of the r constraint for Morello capability registers.
+@ifset INTERNALS
+This is not intended to ever be used in backend patterns.  It only exists to
+enable the compiling of CHERI-specific inline asm.
+@end ifset
+
 @item I
 Integer constant that is valid as an immediate operand in an @code{ADD}
 instruction
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/c-constraint.c b/gcc/testsuite/gcc.target/aarch64/morello/c-constraint.c
new file mode 100644
index 00000000000..eccaccf02bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/morello/c-constraint.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-additional-options "-save-temps" } */
+/* { dg-skip-if "" { *-*-* } { "-mfake-capability" } { "" } }  */
+
+const void * __capability
+foo (const void * __capability c1, void * __capability c2) {
+  void * __capability retval;
+  asm volatile(
+  "	seal	%0, %1, %2\n"
+  : "=C" (retval)
+  : "C" (c1),
+    "C" (c2));
+  return retval;
+}
+
+/* { dg-final { scan-assembler-times {seal\tc[0-9]+, c[0-9]+, c[0-9]+} 1 } } */