[gcc(refs/vendors/ARM/heads/morello)] aarch64: Relax aarch64_simd_mem_operand_p

[gcc(refs/vendors/ARM/heads/morello)] aarch64: Relax aarch64_simd_mem_operand_p

[Matthew Malcomson]

https://gcc.gnu.org/g:3f410e87943391f289e4e2eab8c14dc6b696e058

commit 3f410e87943391f289e4e2eab8c14dc6b696e058
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Wed Apr 20 10:40:41 2022 +0100

    aarch64: Relax aarch64_simd_mem_operand_p
    
    In the testcase, the arm_neon.h expansion code was generating
    intrinsics whose mems had (subreg:DI (reg:CADI …) 0) addresses,
    but these addresses were then rejected by the underlying patterns.
    
    The problem was that the define_expands required the address
    to be a pmode_register_operand (and thus allowed subregs) whereas
    aarch64_simd_mem_operand_p required a REG or a POST_INC address
    (and so disallowed subregs).  IMO it was the latter behaviour
    that was wrong, since the rules for what is a valid base register
    should be the same here as elsewhere.

Diff:
---
 gcc/config/aarch64/aarch64.c                      | 2 +-
 gcc/testsuite/gcc.target/aarch64/morello/simd-1.c | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 72f60497ef3..66db7e14e19 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -19476,7 +19476,7 @@ aarch64_simd_mem_operand_p (rtx op)
 {
   return (MEM_P (op)
 	  && (GET_CODE (XEXP (op, 0)) == POST_INC
-	      || REG_P (XEXP (op, 0)))
+	      || aarch64_base_register_rtx_p (XEXP (op, 0), false))
 	  && aarch64_normal_base_mode_p (mem_address_mode (op)));
 }
 
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/simd-1.c b/gcc/testsuite/gcc.target/aarch64/morello/simd-1.c
new file mode 100644
index 00000000000..b57dc4a27e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/morello/simd-1.c
@@ -0,0 +1,5 @@
+#include <arm_neon.h>
+
+void f(int *__capability x, int32x4x2_t v) {
+  vst2q_s32((int *)x, v);
+}