[gcc(refs/users/meissner/heads/work089)] Delay splitting addti3/subti3 until first split pass.

[gcc(refs/users/meissner/heads/work089)] Delay splitting addti3/subti3 until first split pass.

[Michael Meissner]

https://gcc.gnu.org/g:8d2d4cb828de4861b69b0fb199a4838bc58bf791

commit 8d2d4cb828de4861b69b0fb199a4838bc58bf791
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu May 12 18:29:40 2022 -0400

    Delay splitting addti3/subti3 until first split pass.
    
    This patch makes addti3 and subti3 be define_insn_and_split instead of
    define_expand.  This patch will be a building block to support in a future
    patch PR target/103109 which wants to optimize 128-bit some integer
    multiply-add combinations to use the power9 maddld, maddhd, maddhdu
    instructions.  In order to support recognizing the multiply and add
    combination, we need to keep the addti3 and subti3 as complete insns
    through the combiner phase.
    
    2022-05-12   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * config/rs6000/rs6000.md (addti3): Don't immediately expand the
            insn.  Delay expansion until the split passes.
            (subti3): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000.md | 41 +++++++++++++++++++++++++++++------------
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bf85baa5370..2aba70393d8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7020,12 +7020,19 @@
 ;; allocator from allocating registers that overlap with the inputs
 ;; (for example, having an input in 7,8 and an output in 6,7).  We
 ;; also allow for the output being the same as one of the inputs.
-
-(define_expand "addti3"
-  [(set (match_operand:TI 0 "gpc_reg_operand")
-	(plus:TI (match_operand:TI 1 "gpc_reg_operand")
-		 (match_operand:TI 2 "reg_or_short_operand")))]
+;;
+;; Addti3/subti3 are define_insn_and_splits instead of define_expand, to allow
+;; for combine to make things like multiply and add with extend operations.
+
+(define_insn_and_split "addti3"
+  [(set (match_operand:TI 0 "gpc_reg_operand"               "=&r,r,r")
+	(plus:TI (match_operand:TI 1 "gpc_reg_operand"       "r, 0,r")
+		 (match_operand:TI 2 "reg_or_short_operand"  "rI,r,0")))
+   (clobber (reg:DI CA_REGNO))]
   "TARGET_64BIT"
+  "#"
+  "&& 1"
+  [(pc)]
 {
   rtx lo0 = gen_lowpart (DImode, operands[0]);
   rtx lo1 = gen_lowpart (DImode, operands[1]);
@@ -7042,13 +7049,20 @@
   emit_insn (gen_adddi3_carry (lo0, lo1, lo2));
   emit_insn (gen_adddi3_carry_in (hi0, hi1, hi2));
   DONE;
-})
-
-(define_expand "subti3"
-  [(set (match_operand:TI 0 "gpc_reg_operand")
-	(minus:TI (match_operand:TI 1 "reg_or_short_operand")
-		  (match_operand:TI 2 "gpc_reg_operand")))]
+}
+  [(set_attr "length" "8")
+   (set_attr "type"   "add")
+   (set_attr "size"   "128")])
+
+(define_insn_and_split "subti3"
+  [(set (match_operand:TI 0 "gpc_reg_operand"                "=&r,r,r")
+	(minus:TI (match_operand:TI 1 "reg_or_short_operand" "rI,0,r")
+		  (match_operand:TI 2 "gpc_reg_operand"      "r, r,0")))
+   (clobber (reg:DI CA_REGNO))]
   "TARGET_64BIT"
+  "#"
+  "&& 1"
+  [(pc)]
 {
   rtx lo0 = gen_lowpart (DImode, operands[0]);
   rtx lo1 = gen_lowpart (DImode, operands[1]);
@@ -7065,7 +7079,10 @@
   emit_insn (gen_subfdi3_carry (lo0, lo2, lo1));
   emit_insn (gen_subfdi3_carry_in (hi0, hi2, hi1));
   DONE;
-})
+}
+  [(set_attr "length" "8")
+   (set_attr "type"   "add")
+   (set_attr "size"   "128")])
 \f
 ;; 128-bit logical operations expanders