[gcc(refs/vendors/ARM/heads/morello)] aarch64: Switch to using .chericap rather than .capinit

[gcc(refs/vendors/ARM/heads/morello)] aarch64: Switch to using .chericap rather than .capinit

[Alex Coplan]

https://gcc.gnu.org/g:68416564c49e91572652805fb6addae76d0819a7

commit 68416564c49e91572652805fb6addae76d0819a7
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Fri May 20 17:54:38 2022 +0100

    aarch64: Switch to using .chericap rather than .capinit
    
    .chericap allocates space for the capability automatically rather than
    requiring two .xword 0 lines after every capability directive. This
    should improve the readability of GCC's Morello codegen.
    
    We also update morello tests that look for .capinit in the assembly
    output to look for .chericap instead.

Diff:
---
 gcc/config/aarch64/aarch64.c                                          | 4 ++--
 gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-1.c         | 2 +-
 gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-2.c         | 2 +-
 gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-3.c         | 2 +-
 gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-4.c         | 2 +-
 gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-5.c         | 2 +-
 gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-6.c         | 2 +-
 gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-7.c         | 2 +-
 gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-8.c         | 2 +-
 .../gcc.target/aarch64/morello/label-addressing-includes-lsb.c        | 2 +-
 gcc/testsuite/gcc.target/aarch64/morello/symbol-loading.c             | 4 ++--
 11 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 7974806504a..f49b46fc36b 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -20654,10 +20654,10 @@ aarch64_asm_output_capability (rtx x, unsigned int size, int aligned_p)
     }
   else
     {
-      fputs ("\t.capinit\t", asm_out_file);
+      fputs ("\t.chericap\t", asm_out_file);
       output_addr_const (asm_out_file, x);
       fputc ('\n', asm_out_file);
-      ret = targetm.asm_out.integer (const0_rtx, offset_size, aligned_p);
+      return true;
     }
 
   return ret && targetm.asm_out.integer (const0_rtx, offset_size, aligned_p);
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-1.c b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-1.c
index 175471ef26f..3dc05a8ef75 100644
--- a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-1.c
@@ -17,4 +17,4 @@ __GIMPLE int *__capability foo() {
 }
 
 /* { dg-final { scan-assembler {\t\.section\t\.data\.rel\.ro\.local,"aw"\n\t\.align\t4\n\t\.type\t\.LC0, %object\n} } } */
-/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.capinit\tx\n} } } */
+/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.chericap\tx\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-2.c b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-2.c
index b1a724f2158..415013fa604 100644
--- a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-2.c
@@ -18,4 +18,4 @@ __GIMPLE int *__capability foo() {
 
 /* { dg-final { scan-assembler {\tldr\tc0, \.LC0\n\tret\n} } } */
 /* { dg-final { scan-assembler {\t\.section\t\.data\.rel\.ro,"aw"\n\t\.align\t4\n\t\.type\t\.LC0, %object\n} } } */
-/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.capinit\tx\n} } } */
+/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.chericap\tx\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-3.c b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-3.c
index 512c517c8c4..3c4d80d73b6 100644
--- a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-3.c
+++ b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-3.c
@@ -18,4 +18,4 @@ __GIMPLE int *__capability foo() {
 }
 
 /* { dg-final { scan-assembler {\t\.section\t\.data\.rel\.ro\.local,"aw"\n\t\.align\t4\n\t\.type\t\.LC0, %object\n} } } */
-/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.capinit\tx\n} } } */
+/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.chericap\tx\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-4.c b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-4.c
index 6c75c03cc36..32fff93d26c 100644
--- a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-4.c
+++ b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-4.c
@@ -18,4 +18,4 @@ __GIMPLE int *__capability foo() {
 }
 
 /* { dg-final { scan-assembler {\t\.section\t\.data\.rel\.ro,"aw"\n\t\.align\t4\n\t\.type\t\.LC0, %object\n} } } */
-/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.capinit\tx\n} } } */
+/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.chericap\tx\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-5.c b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-5.c
index 336af2385f9..0a747d46cf7 100644
--- a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-5.c
+++ b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-5.c
@@ -18,4 +18,4 @@ __GIMPLE int *__capability foo() {
 }
 
 /* { dg-final { scan-assembler {\t\.section\t\.data\.rel\.ro\.local,"aw"\n\t\.align\t4\n\t\.type\t\.LC0, %object\n} } } */
-/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.capinit\tx\n} } } */
+/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.chericap\tx\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-6.c b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-6.c
index b2de53702bd..f2086677688 100644
--- a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-6.c
+++ b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-6.c
@@ -18,4 +18,4 @@ __GIMPLE int *__capability foo() {
 }
 
 /* { dg-final { scan-assembler {\t\.section\t\.data\.rel\.ro,"aw"\n\t\.align\t4\n\t\.type\t\.LC0, %object\n} } } */
-/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.capinit\tx\n} } } */
+/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.chericap\tx\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-7.c b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-7.c
index 28815382ad4..daa0ba00832 100644
--- a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-7.c
+++ b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-7.c
@@ -20,4 +20,4 @@ __GIMPLE int *__capability foo() {
 
 /* { dg-final { scan-assembler {\t\.size\t\.LC1, 8\n\.LC1:\n\t\.xword\t\.LC0\n} } } */
 /* { dg-final { scan-assembler {\t\.section\t\.data\.rel\.ro\.local,"aw"\n\t\.align\t4\n\t\.type\t\.LC0, %object\n} } } */
-/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.capinit\tx\n} } } */
+/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.chericap\tx\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-8.c b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-8.c
index e3af4896246..ccbcd9bd826 100644
--- a/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-8.c
+++ b/gcc/testsuite/gcc.target/aarch64/morello/hybrid-addr-expr-8.c
@@ -19,4 +19,4 @@ __GIMPLE int *__capability foo() {
 
 /* { dg-final { scan-assembler {\t\.size\t\.LC1, 8\n\.LC1:\n\t\.xword\t\.LC0\n} } } */
 /* { dg-final { scan-assembler {\t\.section\t\.data\.rel\.ro\.local,"aw"\n\t\.align\t4\n\t\.type\t\.LC0, %object\n} } } */
-/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.capinit\tx\n} } } */
+/* { dg-final { scan-assembler {\t\.size\t\.LC0, 16\n\.LC0:\n\t\.chericap\tx\n} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/label-addressing-includes-lsb.c b/gcc/testsuite/gcc.target/aarch64/morello/label-addressing-includes-lsb.c
index bce89ae42ec..b982e880d97 100644
--- a/gcc/testsuite/gcc.target/aarch64/morello/label-addressing-includes-lsb.c
+++ b/gcc/testsuite/gcc.target/aarch64/morello/label-addressing-includes-lsb.c
@@ -26,7 +26,7 @@ label2:
 }
 
 /* Ensure that we initialise labels in the constant pool with the correct form.  */
-/* { dg-final { scan-assembler {capinit\tfun\+\(\(\.L\d\+\(1\)\)-fun\)} { target cheri_capability_pure } } } */
+/* { dg-final { scan-assembler {chericap\tfun\+\(\(\.L\d\+\(1\)\)-fun\)} { target cheri_capability_pure } } } */
 
 /* Ensure that we load labels directly with the LSB set.  */
 /* { dg-final { scan-assembler {adrp[^\n]*\.L\d\+\(1\)} { target cheri_capability_pure } } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/symbol-loading.c b/gcc/testsuite/gcc.target/aarch64/morello/symbol-loading.c
index ce4e1473b57..d2d3597f155 100644
--- a/gcc/testsuite/gcc.target/aarch64/morello/symbol-loading.c
+++ b/gcc/testsuite/gcc.target/aarch64/morello/symbol-loading.c
@@ -16,10 +16,10 @@ int ret_c() { return c; }
 void modify_just_for_optimisation () { b += 1; }
 
 /* Ensure that we load `b` *indirectly*.  Do this by checking that we do not
-   emit an `adrp` for that symbol and by ensuring that there is a `capinit b`
+   emit an `adrp` for that symbol and by ensuring that there is a `chericap b`
    in the output.  */
 /* { dg-final { scan-assembler-not {adrp[^\n]*b} { target cheri_capability_pure } } } */
-/* { dg-final { scan-assembler {capinit\tb} { target cheri_capability_pure } } } */
+/* { dg-final { scan-assembler {chericap\tb} { target cheri_capability_pure } } } */
 
 /* Ensure that `a` and `c` are accessed through the GOT.  */
 /* { dg-final { scan-assembler {adrp[^\n]*:got:a} { target cheri_capability_pure } } } */