public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc r13-717] RISC-V: Enable TARGET_SUPPORTS_WIDE_INT
@ 2022-05-23 23:32 Palmer Dabbelt
  0 siblings, 0 replies; only message in thread
From: Palmer Dabbelt @ 2022-05-23 23:32 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:ef85d150b59637b6eb116947c1d29e97d562e7db

commit r13-717-gef85d150b59637b6eb116947c1d29e97d562e7db
Author: Vineet Gupta <vineetg@rivosinc.com>
Date:   Mon May 23 16:25:39 2022 -0700

    RISC-V: Enable TARGET_SUPPORTS_WIDE_INT
    
    This is at par with other major arches such as aarch64, i386, s390 ...
    
    gcc/ChangeLog
    
            * config/riscv/predicates.md (const_0_operand): Remove
            const_double.
            * config/riscv/riscv.cc (riscv_rtx_costs): Add check for
            CONST_DOUBLE.
            * config/riscv/riscv.h (TARGET_SUPPORTS_WIDE_INT): New define.
    
    Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
    Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

Diff:
---
 gcc/config/riscv/predicates.md | 2 +-
 gcc/config/riscv/riscv.cc      | 6 ++++++
 gcc/config/riscv/riscv.h       | 2 ++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 97cdbdf053b..40c1c720f1d 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -52,7 +52,7 @@
        (match_test "INTVAL (op) + 1 != 0")))
 
 (define_predicate "const_0_operand"
-  (and (match_code "const_int,const_wide_int,const_double,const_vector")
+  (and (match_code "const_int,const_wide_int,const_vector")
        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 
 (define_predicate "reg_or_0_operand"
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ee756aab694..fb6621464ea 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1797,6 +1797,12 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
     case SYMBOL_REF:
     case LABEL_REF:
     case CONST_DOUBLE:
+      /* With TARGET_SUPPORTS_WIDE_INT const int can't be in CONST_DOUBLE
+	 rtl object. Weird recheck due to switch-case fall through above.  */
+      if (GET_CODE (x) == CONST_DOUBLE)
+	gcc_assert (GET_MODE (x) != VOIDmode);
+      /* Fall through.  */
+
     case CONST:
       if ((cost = riscv_const_insns (x)) > 0)
 	{
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index b191606edb4..5083a1c24b0 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1009,4 +1009,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
 
+#define TARGET_SUPPORTS_WIDE_INT 1
+
 #endif /* ! GCC_RISCV_H */


^ permalink raw reply	[flat|nested] only message in thread

only message in thread, other threads:[~2022-05-23 23:32 UTC | newest]

Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-23 23:32 [gcc r13-717] RISC-V: Enable TARGET_SUPPORTS_WIDE_INT Palmer Dabbelt

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).