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* [gcc r11-10030] Daily bump.
@ 2022-05-25 0:19 GCC Administrator
0 siblings, 0 replies; only message in thread
From: GCC Administrator @ 2022-05-25 0:19 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7a92b36ecb4e760fe358d7c6b1001361e0ebacca
commit r11-10030-g7a92b36ecb4e760fe358d7c6b1001361e0ebacca
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Wed May 25 00:18:37 2022 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 12 ++++++++++++
gcc/DATESTAMP | 2 +-
gcc/testsuite/ChangeLog | 37 +++++++++++++++++++++++++++++++++++++
3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 717051909ab..343b1d49b39 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2022-05-24 Qing Zhao <qing.zhao@oracle.com>
+
+ Backported from master:
+ 2022-05-09 Qing Zhao <qing.zhao@oracle.com>
+
+ PR target/101891
+ * config/i386/i386.c (zero_call_used_regno_mode): use V2SImode
+ as a generic MMX mode instead of V4HImode.
+ (zero_all_mm_registers): Use SET to zero instead of MOV for
+ zeroing scratch registers.
+ (ix86_zero_call_used_regs): Likewise.
+
2022-05-23 Paul A. Clarke <pc@us.ibm.com>
PR target/104257
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7d93d3872a3..a0acbbdde33 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20220524
+20220525
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index fbec5caf201..8acc0ef0050 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,40 @@
+2022-05-24 Qing Zhao <qing.zhao@oracle.com>
+
+ Backported from master:
+ 2022-05-09 Qing Zhao <qing.zhao@oracle.com>
+
+ * gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector
+ -fno-PIC.
+ * gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor.
+ * gcc.target/i386/zero-scratch-regs-13.c: Add -msse.
+ * gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor.
+ * gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector
+ -fno-PIC.
+ * gcc.target/i386/zero-scratch-regs-16.c: Likewise.
+ * gcc.target/i386/zero-scratch-regs-17.c: Likewise.
+ * gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector
+ -fno-PIC, adjust mov to xor.
+ * gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector
+ -fno-PIC.
+ * gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor.
+ * gcc.target/i386/zero-scratch-regs-20.c: Add -msse.
+ * gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector
+ -fno-PIC, Adjust mov to xor.
+ * gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor.
+ * gcc.target/i386/zero-scratch-regs-23.c: Likewise.
+ * gcc.target/i386/zero-scratch-regs-26.c: Likewise.
+ * gcc.target/i386/zero-scratch-regs-27.c: Likewise.
+ * gcc.target/i386/zero-scratch-regs-28.c: Likewise.
+ * gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector.
+ * gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor.
+ * gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector
+ -fno-PIC.
+ * gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor.
+ * gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector.
+ * gcc.target/i386/zero-scratch-regs-7.c: Likewise.
+ * gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor.
+ * gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector.
+
2022-05-19 Michael Meissner <meissner@linux.ibm.com>
Backported from master:
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