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* [gcc(refs/users/meissner/heads/work090)] Revert patch.
@ 2022-06-03 17:13 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2022-06-03 17:13 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:28ce29f5dafcd2c154517d6c8b30bcb09967dc1d
commit 28ce29f5dafcd2c154517d6c8b30bcb09967dc1d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jun 3 13:12:53 2022 -0400
Revert patch.
2022-06-03 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
Revert patch.
* gcc.target/powerpc/mma-builtin-1.c: Eliminate checking for store
vector pair instructions.
* gcc.target/powerpc/mma-builtin-10-pair.c: Likewise.
* gcc.target/powerpc/mma-builtin-10-quit.c: Likewise.
* gcc.target/powerpc/mma-builtin-2.c: Likewise.
* gcc.target/powerpc/mma-builtin-3.c: Likewise.
* gcc.target/powerpc/mma-builtin-4.c: Likewise.
* gcc.target/powerpc/mma-builtin-5.c: Likewise.
* gcc.target/powerpc/mma-builtin-6.c: Likewise.
* gcc.target/powerpc/mma-builtin-7.c: Likewise.
* gcc.target/powerpc/mma-builtin-9.c: Likewise.
* gcc.target/powerpc/mma-builtin-8.c: Add -mstore-vector-pair.
* gcc.target/powerpc/pr102976.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c | 1 +
gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c | 1 +
gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c | 1 +
gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c | 1 +
gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c | 1 +
gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c | 1 +
gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c | 1 +
gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c | 1 +
gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c | 1 +
gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c | 1 +
gcc/testsuite/gcc.target/powerpc/pr102976.c | 6 +-----
12 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c
index 47b45b00403..69ee826e1be 100644
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c
@@ -260,6 +260,7 @@ foo13b (__vector_quad *dst, __vector_quad *src, vec_t *vec)
/* { dg-final { scan-assembler-times {\mlxv\M} 40 } } */
/* { dg-final { scan-assembler-times {\mlxvp\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 40 } } */
/* { dg-final { scan-assembler-times {\mxxmfacc\M} 20 } } */
/* { dg-final { scan-assembler-times {\mxxmtacc\M} 6 } } */
/* { dg-final { scan-assembler-times {\mxvbf16ger2\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c
index 26f7868c00d..d8748d8e7d0 100644
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c
@@ -18,3 +18,4 @@ foo (__vector_pair *dst, vec_t *src)
/* { dg-final { scan-assembler-not {\mlxv\M} } } */
/* { dg-final { scan-assembler-not {\mstxv\M} } } */
/* { dg-final { scan-assembler-times {\mlxvp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c
index 0d5f54c7825..02342c76f5f 100644
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c
@@ -20,3 +20,4 @@ foo (__vector_quad *dst, vec_t *src)
/* { dg-final { scan-assembler-times {\mlxvp\M} 4 } } */
/* { dg-final { scan-assembler-times {\mxxmtacc\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxmfacc\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c
index 5943702d8f3..0230d727657 100644
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c
@@ -59,6 +59,7 @@ foo3 (__vector_quad *dst, __vector_quad *src, vec_t *vec, __vector_pair *pvecp)
/* { dg-final { scan-assembler-times {\mxxmtacc\M} 2 } } */
/* { dg-final { scan-assembler-times {\mlxv\M} 4 } } */
/* { dg-final { scan-assembler-times {\mlxvp\M} 8 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 8 } } */
/* { dg-final { scan-assembler-times {\mxvf64ger\M} 1 } } */
/* { dg-final { scan-assembler-times {\mxvf64gerpp\M} 1 } } */
/* { dg-final { scan-assembler-times {\mxvf64gerpn\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c
index ee65ef9d96f..9bec78d333f 100644
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c
@@ -26,5 +26,6 @@ foo1 (vec_t *vec)
/* { dg-final { scan-assembler-times {\mlxv\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxv\M} 2 } } */
/* { dg-final { scan-assembler-not {\mlxvp\M} } } */
+/* { dg-final { scan-assembler-not {\mstxvp\M} } } */
/* { dg-final { scan-assembler-times {\mxvcvspbf16\M} 1 } } */
/* { dg-final { scan-assembler-times {\mxvcvbf16spn\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c
index b67cb42b3b9..a9fb0107d12 100644
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c
@@ -69,4 +69,5 @@ bar2 (vec_t *dst, __vector_pair *src)
/* { dg-final { scan-assembler-times {\mlxv\M} 6 } } */
/* { dg-final { scan-assembler-times {\mlxvp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxv\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c
index df0a6838c66..00503b7343d 100644
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c
@@ -42,5 +42,6 @@ bar (vec_t *dst, __vector_quad *src)
/* { dg-final { scan-assembler-times {\mlxv\M} 8 } } */
/* { dg-final { scan-assembler-times {\mlxvp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mstxv\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */
/* { dg-final { scan-assembler-times {\mxxmfacc\M} 3 } } */
/* { dg-final { scan-assembler-times {\mxxmtacc\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c
index 2f5747da070..715b28138e9 100644
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c
@@ -17,3 +17,4 @@ foo (__vector_quad *dst)
/* { dg-final { scan-assembler-not {\mxxmtacc\M} } } */
/* { dg-final { scan-assembler-times {\mxxsetaccz\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxmfacc\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c
index 77d86c37f97..c661a4b84bc 100644
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c
@@ -23,3 +23,4 @@ foo (__vector_pair *dst, __vector_pair *src, long idx)
/* { dg-final { scan-assembler-times {\mlxvp\M} 3 } } */
/* { dg-final { scan-assembler-times {\mlxvpx\M} 1 } } */
/* { dg-final { scan-assembler-times {\mplxvp\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c
index cbd2e6dbae1..af29e479f83 100644
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mstore-vector-pair" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
void
foo (__vector_pair *dst, __vector_pair *src, long idx)
diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c
index 94e6d4016c5..397d0f1db35 100644
--- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c
+++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c
@@ -25,3 +25,4 @@ bar (__vector_quad *dst, vec_t *src)
/* { dg-final { scan-assembler-not {\mlxv\M} } } */
/* { dg-final { scan-assembler-not {\mstxv\M} } } */
/* { dg-final { scan-assembler-times {\mlxvp\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mstxvp\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr102976.c b/gcc/testsuite/gcc.target/powerpc/pr102976.c
index c975eba86da..5a4320f8e0a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr102976.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr102976.c
@@ -1,11 +1,7 @@
/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10 -mstore-vector-pair" } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
#include <altivec.h>
-
-/* The test relies on store vector pair being generated. Otherwise, it
- will generate 2 stxv instructions. */
-
void
bug (__vector_pair *dst)
{
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work090)] Revert patch.
@ 2022-06-06 19:15 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2022-06-06 19:15 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:87d32c4ecace058211da00f5aced93c1ac9e7353
commit 87d32c4ecace058211da00f5aced93c1ac9e7353
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Jun 6 15:14:09 2022 -0400
Revert patch.
2022-06-06 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
PR target/99293
* config/rs6000/rs6000-p8swap.cc (rtx_is_swappable_p): Remove
UNSPEC_VSX_XXSPLTD case.
* config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTD): Delete.
(vsx_xxspltd_<mode>): Rewrite to use VEC_DUPLICATE.
* ChangeLog.meissner: Undo changes.
gcc/testsuite:
Revert patch.
PR target/99293
* gcc.target/powerpc/builtins-1.c: Update insn count.
* gcc.target/powerpc/pr99293.c: New test.
Diff:
---
gcc/ChangeLog.meissner | 90 ---------------------------
gcc/config/rs6000/rs6000-p8swap.cc | 1 +
gcc/config/rs6000/vsx.md | 19 +++---
gcc/testsuite/gcc.target/powerpc/builtins-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr99293.c | 46 --------------
5 files changed, 11 insertions(+), 147 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 421d8fbff94..b21240d0afc 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,93 +1,3 @@
-==================== work090 patch #4
-
-Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293.
-
-This is version 3 of the patch. The original patch was:
-
-| Date: Mon, 28 Mar 2022 12:26:02 -0400
-| Subject: [PATCH 1/4] Optimize vec_splats of constant vec_extract for V2DI/V2DF, PR target 99293.
-| Message-ID: <YkHhmvwSJF7DUDhJ@toto.the-meissners.org>
-| https://gcc.gnu.org/pipermail/gcc-patches/2022-March/592420.html
-
-Version 2 of the patch was:
-
-| Date: Fri, 13 May 2022 10:49:26 -0400
-| Subject: [PATCH] Optimize vec_splats of constant V2DI/V2DF vec_extract, PR target/99293
-| Message-ID: <Yn5v9kqBaETg0roR@toto.the-meissners.org>
-| https://gcc.gnu.org/pipermail/gcc-patches/2022-May/594797.html
-
-In PR target/99293, it was pointed out that doing:
-
- vector long long dest0, dest1, src;
- /* ... */
- dest0 = vec_splats (vec_extract (src, 0));
- dest1 = vec_splats (vec_extract (src, 1));
-
-would generate slower code.
-
-It generates the following code on power8:
-
- ;; vec_splats (vec_extract (src, 0))
- xxpermdi 0,34,34,3
- xxpermdi 34,0,0,0
-
- ;; vec_splats (vec_extract (src, 1))
- xxlor 0,34,34
- xxpermdi 34,0,0,0
-
-However on power9 and power10 it generates:
-
- ;; vec_splats (vec_extract (src, 0))
- mfvsld 3,34
- mtvsrdd 34,9,9
-
- ;; vec_splats (vec_extract (src, 1))
- mfvsrd 9,34
- mtvsrdd 34,9,9
-
-This is due to the power9 having the mfvsrld instruction which can extract
-either 64-bit element into a GPR. While there are alternatives for both
-vector registers and GPR registers, the register allocator prefers to put
-DImode into GPR registers.
-
-In this case, it is better to have a single combiner pattern that can generate
-a single xxpermdi, instead of 2 insnsns (the extract and then the concat).
-This is true if the two operations are move from vector register and move to
-vector register. As Segher pointed out in a previous version of the patch, the
-combiner already tries doing creating a (vec_duplicate (vec_select ...))
-pattern, but we didn't provide one.
-
-This patch reworks vsx_xxspltd_<mode> for V2DImode and V2DFmode so that it now
-uses VEC_DUPLICATE, which the combiner checks for.
-
-I have built Spec 2017 with this patch installed, and the cam4_r benchmark
-is the only benchmark that generated different code (3 mfvsrld/mtvsrdd
-pairs of instructions were replaced with xxpermdi).
-
-I have built bootstrap versions on the following systems and I have run
-the regression tests. There were no regressions in the runs:
-
- Power9 little endian, --with-cpu=power9
- Power10 little endian, --with-cpu=power10
- Power8 big endian, --with-cpu=power8 (both 32-bit & 64-bit tests)
-
-Can I install this into the trunk? After a burn-in period, can I backport
-and install this into GCC 11 and GCC 10 branches?
-
-2022-06-06 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
- PR target/99293
- * config/rs6000/rs6000-p8swap.cc (rtx_is_swappable_p): Remove
- UNSPEC_VSX_XXSPLTD case.
- * config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTD): Delete.
- (vsx_xxspltd_<mode>): Rewrite to use VEC_DUPLICATE.
-
-gcc/testsuite:
- PR target/99293
- * gcc.target/powerpc/builtins-1.c: Update insn count.
- * gcc.target/powerpc/pr99293.c: New test.
-
==================== work090 patch #3
Adjust MMA tests to account for no store vector pair.
diff --git a/gcc/config/rs6000/rs6000-p8swap.cc b/gcc/config/rs6000/rs6000-p8swap.cc
index 3160fcbdeca..275702fee1b 100644
--- a/gcc/config/rs6000/rs6000-p8swap.cc
+++ b/gcc/config/rs6000/rs6000-p8swap.cc
@@ -807,6 +807,7 @@ rtx_is_swappable_p (rtx op, unsigned int *special)
case UNSPEC_VUPKLU_V4SF:
return 0;
case UNSPEC_VSPLT_DIRECT:
+ case UNSPEC_VSX_XXSPLTD:
*special = SH_SPLAT;
return 1;
case UNSPEC_REDUC_PLUS:
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a1a1ce95195..1b75538f42f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -296,6 +296,7 @@
UNSPEC_VSX_XXPERM
UNSPEC_VSX_XXSPLTW
+ UNSPEC_VSX_XXSPLTD
UNSPEC_VSX_DIVSD
UNSPEC_VSX_DIVUD
UNSPEC_VSX_DIVSQ
@@ -4672,18 +4673,16 @@
;; V2DF/V2DI splat for use by vec_splat builtin
(define_insn "vsx_xxspltd_<mode>"
[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
- (vec_duplicate:VSX_D
- (vec_select:<VS_scalar>
- (match_operand:VSX_D 1 "gpc_reg_operand" "wa")
- (parallel [(match_operand:QI 2 "const_0_to_1_operand" "i")]))))]
+ (unspec:VSX_D [(match_operand:VSX_D 1 "vsx_register_operand" "wa")
+ (match_operand:QI 2 "u5bit_cint_operand" "i")]
+ UNSPEC_VSX_XXSPLTD))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
- HOST_WIDE_INT dword = INTVAL (operands[2]);
- if (!BYTES_BIG_ENDIAN)
- dword = !dword;
-
- operands[3] = GEN_INT (3*dword);
- return "xxpermdi %x0,%x1,%x1,%3";
+ if ((BYTES_BIG_ENDIAN && INTVAL (operands[2]) == 0)
+ || (!BYTES_BIG_ENDIAN && INTVAL (operands[2]) == 1))
+ return "xxpermdi %x0,%x1,%x1,0";
+ else
+ return "xxpermdi %x0,%x1,%x1,3";
}
[(set_attr "type" "vecperm")])
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
index 98783668bce..28cd1aa6b1a 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
@@ -1035,4 +1035,4 @@ foo156 (vector unsigned short usa)
/* { dg-final { scan-assembler-times {\mvmrglb\M} 3 } } */
/* { dg-final { scan-assembler-times {\mvmrgew\M} 4 } } */
/* { dg-final { scan-assembler-times {\mvsplth|xxsplth\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mxxpermdi\M} 42 } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 44 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr99293.c b/gcc/testsuite/gcc.target/powerpc/pr99293.c
deleted file mode 100644
index 6a06962a001..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr99293.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx" } */
-
-/* Test for PR 99263, which wants to do:
- __builtin_vec_splats (__builtin_vec_extract (v, n))
-
- where v is a V2DF or V2DI vector and n is either 0 or 1.
-
- Previously for:
- __builtin_vec_splats (__builtin_vec_extract (v, 0));
-
- GCC would generate:
-
- mfvsrld 9,34
- mtvsrdd 34,9,9
-
- Now it generates:
-
- xxpermdi 34,34,34,3. */
-
-vector long long
-splat_dup_ll_0 (vector long long v)
-{
- return __builtin_vec_splats (__builtin_vec_extract (v, 0));
-}
-
-vector long long
-splat_dup_ll_1 (vector long long v)
-{
- return __builtin_vec_splats (__builtin_vec_extract (v, 1));
-}
-
-vector double
-splat_dup_d_0 (vector double v)
-{
- return __builtin_vec_splats (__builtin_vec_extract (v, 0));
-}
-
-vector double
-splat_dup_d_1 (vector double v)
-{
- return __builtin_vec_splats (__builtin_vec_extract (v, 1));
-}
-
-/* { dg-final { scan-assembler-times {\mxxpermdi\M} 4 } } */
^ permalink raw reply [flat|nested] 2+ messages in thread
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