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* [gcc r13-1087] RISC-V: add consecutive_bits_operand predicate
@ 2022-06-14 11:38 Philipp Tomsich
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From: Philipp Tomsich @ 2022-06-14 11:38 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:4bf0dcb0492c40be7e0603b13a8b5949609388dd
commit r13-1087-g4bf0dcb0492c40be7e0603b13a8b5949609388dd
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Tue May 24 15:03:47 2022 +0200
RISC-V: add consecutive_bits_operand predicate
Provide an easy way to constrain for constants that are a a single,
consecutive run of ones.
gcc/ChangeLog:
* config/riscv/predicates.md (consecutive_bits_operand):
Implement new predicate.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Diff:
---
gcc/config/riscv/predicates.md | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index c37caa2502b..90db5dfcdd5 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -243,3 +243,14 @@
(define_predicate "imm5_operand"
(and (match_code "const_int")
(match_test "INTVAL (op) < 5")))
+
+;; A CONST_INT operand that consists of a single run of consecutive set bits.
+(define_predicate "consecutive_bits_operand"
+ (match_code "const_int")
+{
+ unsigned HOST_WIDE_INT val = UINTVAL (op);
+ if (exact_log2 ((val >> ctz_hwi (val)) + 1) < 0)
+ return false;
+
+ return true;
+})
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