[gcc r12-8482] Fix ICE in extract_insn, at recog.cc:2791

[gcc r12-8482] Fix ICE in extract_insn, at recog.cc:2791

[hongtao Liu]

https://gcc.gnu.org/g:bac09a893145056217b1e9a0054466a770815c43

commit r12-8482-gbac09a893145056217b1e9a0054466a770815c43
Author: liuhongt <hongtao.liu@intel.com>
Date:   Tue Jun 14 16:27:04 2022 +0800

    Fix ICE in extract_insn, at recog.cc:2791
    
    (In reply to Uroš Bizjak from comment #1)
    > Instruction does not accept memory operand for operand 3:
    >
    > (define_insn_and_split
    > "*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_ltint"
    >   [(set (match_operand:<ssebytemode> 0 "register_operand" "=Yr,*x,x")
    >       (unspec:<ssebytemode>
    >         [(match_operand:<ssebytemode> 1 "register_operand" "0,0,x")
    >          (match_operand:<ssebytemode> 2 "vector_operand" "YrBm,*xBm,xm")
    >          (subreg:<ssebytemode>
    >            (lt:VI48_AVX
    >              (match_operand:VI48_AVX 3 "register_operand" "Yz,Yz,x")
    >              (match_operand:VI48_AVX 4 "const0_operand")) 0)]
    >         UNSPEC_BLENDV))]
    >
    > The problematic insn is:
    >
    > (define_insn_and_split "*avx_cmp<mode>3_ltint_not"
    >  [(set (match_operand:VI48_AVX  0 "register_operand")
    >        (vec_merge:VI48_AVX
    >        (match_operand:VI48_AVX 1 "vector_operand")
    >        (match_operand:VI48_AVX 2 "vector_operand")
    >        (unspec:<avx512fmaskmode>
    >          [(subreg:VI48_AVX
    >           (not:<ssebytemode>
    >             (match_operand:<ssebytemode> 3 "vector_operand")) 0)
    >           (match_operand:VI48_AVX 4 "const0_operand")
    >           (match_operand:SI 5 "const_0_to_7_operand")]
    >           UNSPEC_PCMP)))]
    >
    > which gets split to the above pattern.
    >
    > In the preparation statements we have:
    >
    >   if (!MEM_P (operands[3]))
    >     operands[3] = force_reg (<ssebytemode>mode, operands[3]);
    >   operands[3] = lowpart_subreg (<MODE>mode, operands[3], <ssebytemode>mode);
    >
    > Which won't fly when operand 3 is memory operand...
    >
    
    gcc/ChangeLog:
    
            PR target/105953
            * config/i386/sse.md (*avx_cmp<mode>3_ltint_not): Force_reg
            operands[3].
    
    gcc/testsuite/ChangeLog:
    
            * g++.target/i386/pr105953.C: New test.

Diff:
---
 gcc/config/i386/sse.md                   | 3 +--
 gcc/testsuite/g++.target/i386/pr105953.C | 4 ++++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 3a3ea609fda..2ce1aed4ad9 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -3627,8 +3627,7 @@
 			  gen_lowpart (<ssebytemode>mode, operands[1]));
   operands[2] = gen_lowpart (<ssebytemode>mode, operands[2]);
 
-  if (!MEM_P (operands[3]))
-    operands[3] = force_reg (<ssebytemode>mode, operands[3]);
+  operands[3] = force_reg (<ssebytemode>mode, operands[3]);
   operands[3] = lowpart_subreg (<MODE>mode, operands[3], <ssebytemode>mode);
 })
 
diff --git a/gcc/testsuite/g++.target/i386/pr105953.C b/gcc/testsuite/g++.target/i386/pr105953.C
new file mode 100644
index 00000000000..b423d2dfdae
--- /dev/null
+++ b/gcc/testsuite/g++.target/i386/pr105953.C
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512vl -mabi=ms" } */
+
+#include "pr100738-1.C"