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* [gcc r13-1245] [PATCH,RS6000 2/5] Rework the RS6000_BTM defines.
@ 2022-06-24 14:21 Will Schmidt
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From: Will Schmidt @ 2022-06-24 14:21 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0c0d2b63a706d5282948c18246b10e7c2ffd62fd
commit r13-1245-g0c0d2b63a706d5282948c18246b10e7c2ffd62fd
Author: Will Schmidt <will_schmidt@vnet.ibm.com>
Date: Thu Jun 23 15:48:21 2022 -0500
[PATCH,RS6000 2/5] Rework the RS6000_BTM defines.
The RS6000_BTM_<xxxx> definitions are mostly unused after the rs6000
builtin code was reworked. The remaining references can be replaced
with the OPTION_MASK_<xxxx> and MASK_<xxxx> equivalents.
This patch remvoes the defines:
RS6000_BTM_FRES, RS6000_BTM_FRSQRTE, RS6000_BTM_FRSQRTES,
RS6000_BTM_POPCNTD, RS6000_BTM_CELL, RS6000_BTM_DFP,
RS6000_BTM_HARD_FLOAT, RS6000_BTM_LDBL128, RS6000_BTM_64BIT,
RS6000_BTM_POWERPC64, RS6000_BTM_FLOAT128, RS6000_BTM_FLOAT128_HW
RS6000_BTM_MMA, RS6000_BTM_P10.
I note that the BTM -> OPTION_MASK mappings are not always 1-to-1.
in particular the BTM_FRES and BTM_FRSQRTE values were both mapped to
OPTION_MASK_PPC_GFXOPT, while the BTM_FRE and BTM_FRSQRTES both mapped
to OPTION_MASK_POPCNTB. In total I spent quite a bit of time
double-checking these since it looked like copy/paste errors. I split
some of these changes out into a subsequent patch to limit the amount
of potential confusion in any particular patch.
gcc/
* config/rs6000/rs6000-c.cc: Update comments.
* config/rs6000/rs6000.cc (RS6000_BTM_FRES, RS6000_BTM_FRSQRTE,
RS6000_BTM_FRSQRTES, RS6000_BTM_POPCNTD, RS6000_BTM_CELL,
RS6000_BTM_64BIT, RS6000_BTM_POWERPC64, RS6000_BTM_DFP,
RS6000_BTM_HARD_FLOAT,RS6000_BTM_LDBL128, RS6000_BTM_FLOAT128,
RS6000_BTM_FLOAT128_HW, RS6000_BTM_MMA, RS6000_BTM_P10): Replace
with OPTION_MASK_PPC_GFXOPT, OPTION_MASK_PPC_GFXOPT,
OPTION_MASK_POPCNTB, OPTION_MASK_POPCNTD,
OPTION_MASK_FPRND, MASK_64BIT, MASK_POWERPC64,
OPTION_MASK_DFP, OPTION_MASK_SOFT_FLOAT, OPTION_MASK_MULTIPLE,
OPTION_MASK_FLOAT128_KEYWORD, OPTION_MASK_FLOAT128_HW,
OPTION_MASK_MMA, OPTION_MASK_POWER10.
* config/rs6000/rs6000.h (RS6000_BTM_FRES, RS6000_BTM_FRSQRTE,
RS6000_BTM_FRSQRTES, RS6000_BTM_POPCNTD, RS6000_BTM_CELL,
RS6000_BTM_DFP, RS6000_BTM_HARD_FLOAT, RS6000_BTM_LDBL128,
RS6000_BTM_64BIT, RS6000_BTM_POWERPC64, RS6000_BTM_FLOAT128,
RS6000_BTM_FLOAT128_HW, RS6000_BTM_MMA, RS6000_BTM_P10): Delete.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 6 ++---
gcc/config/rs6000/rs6000.cc | 54 +++++++++++++++++++++----------------------
gcc/config/rs6000/rs6000.h | 14 -----------
3 files changed, 30 insertions(+), 44 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 9c8cbd7a66e..4c99afc761a 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -596,9 +596,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags,
rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__");
/* options from the builtin masks. */
- /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu ==
- PROCESSOR_CELL) (e.g. -mcpu=cell). */
- if ((bu_mask & RS6000_BTM_CELL) != 0)
+ /* Note that OPTION_MASK_FPRND is enabled only if
+ (rs6000_cpu == PROCESSOR_CELL) (e.g. -mcpu=cell). */
+ if ((bu_mask & OPTION_MASK_FPRND) != 0)
rs6000_define_or_undefine_macro (define_p, "__PPU__");
/* Tell the user if we support the MMA instructions. */
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 3d1f895ebd5..092d8e6cbe6 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -3383,28 +3383,28 @@ rs6000_builtin_mask_calculate (void)
| ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
| ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
| ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
- | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
- | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
- | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
- | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
- | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
+ | ((TARGET_FRES) ? OPTION_MASK_PPC_GFXOPT : 0)
+ | ((TARGET_FRSQRTE) ? OPTION_MASK_PPC_GFXOPT : 0)
+ | ((TARGET_FRSQRTES) ? OPTION_MASK_POPCNTB : 0)
+ | ((TARGET_POPCNTD) ? OPTION_MASK_POPCNTD : 0)
+ | ((rs6000_cpu == PROCESSOR_CELL) ? OPTION_MASK_FPRND : 0)
| ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
| ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
| ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
| ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
- | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
- | ((TARGET_POWERPC64) ? RS6000_BTM_POWERPC64 : 0)
+ | ((TARGET_64BIT) ? MASK_64BIT : 0)
+ | ((TARGET_POWERPC64) ? MASK_POWERPC64 : 0)
| ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
| ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
- | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
- | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
+ | ((TARGET_DFP) ? OPTION_MASK_DFP : 0)
+ | ((TARGET_HARD_FLOAT) ? OPTION_MASK_SOFT_FLOAT : 0)
| ((TARGET_LONG_DOUBLE_128
&& TARGET_HARD_FLOAT
- && !TARGET_IEEEQUAD) ? RS6000_BTM_LDBL128 : 0)
- | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
- | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0)
- | ((TARGET_MMA) ? RS6000_BTM_MMA : 0)
- | ((TARGET_POWER10) ? RS6000_BTM_P10 : 0));
+ && !TARGET_IEEEQUAD) ? OPTION_MASK_MULTIPLE : 0)
+ | ((TARGET_FLOAT128_TYPE) ? OPTION_MASK_FLOAT128_KEYWORD : 0)
+ | ((TARGET_FLOAT128_HW) ? OPTION_MASK_FLOAT128_HW : 0)
+ | ((TARGET_MMA) ? OPTION_MASK_MMA : 0)
+ | ((TARGET_POWER10) ? OPTION_MASK_POWER10 : 0));
}
/* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
@@ -24056,24 +24056,24 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
{ "altivec", RS6000_BTM_ALTIVEC, false, false },
{ "vsx", RS6000_BTM_VSX, false, false },
{ "fre", RS6000_BTM_FRE, false, false },
- { "fres", RS6000_BTM_FRES, false, false },
- { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
- { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
- { "popcntd", RS6000_BTM_POPCNTD, false, false },
- { "cell", RS6000_BTM_CELL, false, false },
+ { "fres", OPTION_MASK_PPC_GFXOPT, false, false },
+ { "frsqrte", OPTION_MASK_PPC_GFXOPT, false, false },
+ { "frsqrtes", OPTION_MASK_POPCNTB, false, false },
+ { "popcntd", OPTION_MASK_POPCNTD, false, false },
+ { "cell", OPTION_MASK_FPRND, false, false },
{ "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
{ "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
{ "power9-misc", RS6000_BTM_P9_MISC, false, false },
{ "crypto", RS6000_BTM_CRYPTO, false, false },
{ "htm", RS6000_BTM_HTM, false, false },
- { "hard-dfp", RS6000_BTM_DFP, false, false },
- { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
- { "long-double-128", RS6000_BTM_LDBL128, false, false },
- { "powerpc64", RS6000_BTM_POWERPC64, false, false },
- { "float128", RS6000_BTM_FLOAT128, false, false },
- { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
- { "mma", RS6000_BTM_MMA, false, false },
- { "power10", RS6000_BTM_P10, false, false },
+ { "hard-dfp", OPTION_MASK_DFP, false, false },
+ { "hard-float", OPTION_MASK_SOFT_FLOAT, false, false },
+ { "long-double-128", OPTION_MASK_MULTIPLE, false, false },
+ { "powerpc64", MASK_POWERPC64, false, false },
+ { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, false },
+ { "float128-hw", OPTION_MASK_FLOAT128_HW,false, false },
+ { "mma", OPTION_MASK_MMA, false, false },
+ { "power10", OPTION_MASK_POWER10, false, false },
};
/* Option variables that we want to support inside attribute((target)) and
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 2ff17a16e43..384c5f1599a 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2253,20 +2253,6 @@ extern int frame_pointer_needed;
#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
-#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
-#define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
-#define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
-#define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
-#define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
-#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
-#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
-#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
-#define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
-#define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */
-#define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */
-#define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */
-#define RS6000_BTM_MMA MASK_MMA /* ISA 3.1 MMA. */
-#define RS6000_BTM_P10 MASK_POWER10
enum rs6000_builtin_type_index
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2022-06-24 14:21 [gcc r13-1245] [PATCH,RS6000 2/5] Rework the RS6000_BTM defines Will Schmidt
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