[gcc r13-1313] rs6000: Simplify *rotl<mode>3_insert_4 by removing DImode

[gcc r13-1313] rs6000: Simplify *rotl<mode>3_insert_4 by removing DImode

[Kewen Lin]

https://gcc.gnu.org/g:f9764ea128c99ba1c10de21a092266cd7da8700a

commit r13-1313-gf9764ea128c99ba1c10de21a092266cd7da8700a
Author: Kewen Lin <linkw@linux.ibm.com>
Date:   Mon Jun 27 21:50:26 2022 -0500

    rs6000: Simplify *rotl<mode>3_insert_4 by removing DImode
    
    define_insn *rotl<mode>3_insert_4 use mode iterator GPR which
    consists of SImode and conditional DImode, but the condition
    of this define_insn requires the mode should be SImode.  By
    further checking, it's found that the rldimi instruction can
    not be used for this pattern since the required mask can not
    be represented correctly.  We can have the fixed mask end 31
    with rlwimi, but can not have the fixed mask end 63 with
    rldimi as it has to be (63 - SH) always.
    
    So this patch simplifies this define_insn to use SImode only.
    
    gcc/ChangeLog:
    
            * config/rs6000/rs6000.md (*rotl<mode>3_insert_4): Replace mode
            iterator GPR with SImode, adjust the condition and output template,
            rename to ...
            (*rotlsi3_insert_4): ... this.

Diff:
---
 gcc/config/rs6000/rs6000.md | 25 ++++++++-----------------
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 090dbcff61d..1367a2cb779 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4225,23 +4225,14 @@
   operands[4] = GEN_INT ((HOST_WIDE_INT_1U << INTVAL (operands[2])) - 1);
 })
 
-(define_insn "*rotl<mode>3_insert_4"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-	(ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0")
-			  (match_operand:GPR 4 "const_int_operand" "n"))
-		 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-			       (match_operand:SI 2 "const_int_operand" "n"))))]
-  "<MODE>mode == SImode &&
-   GET_MODE_PRECISION (<MODE>mode)
-   == INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4]))"
-{
-  operands[2] = GEN_INT (GET_MODE_PRECISION (<MODE>mode)
-			 - INTVAL (operands[2]));
-  if (<MODE>mode == SImode)
-    return "rlwimi %0,%1,%h2,32-%h2,31";
-  else
-    return "rldimi %0,%1,%H2,64-%H2";
-}
+(define_insn "*rotlsi3_insert_4"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "0")
+			(match_operand:SI 4 "const_int_operand" "n"))
+		(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			     (match_operand:SI 2 "const_int_operand" "n"))))]
+  "INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4])) == 32"
+  "rlwimi %0,%1,32-%h2,%h2,31"
   [(set_attr "type" "insert")])
 
 (define_insn "*rotlsi3_insert_5"