[gcc r13-1380] PR target/106122: Don't update %esp via the stack with -Oz on x86.

[gcc r13-1380] PR target/106122: Don't update %esp via the stack with -Oz on x86.

[Roger Sayle]

https://gcc.gnu.org/g:17419b61edd350147b0cc10c3da0b8461e51a42c

commit r13-1380-g17419b61edd350147b0cc10c3da0b8461e51a42c
Author: Roger Sayle <roger@nextmovesoftware.com>
Date:   Fri Jul 1 09:18:07 2022 +0100

    PR target/106122: Don't update %esp via the stack with -Oz on x86.
    
    When optimizing for size with -Oz, setting a register can be minimized by
    pushing an immediate value to the stack and popping it to the destination.
    Alas the one general register that shouldn't be updated via the stack is
    the stack pointer itself, where "pop %esp" can't be represented in GCC's
    RTL ("use of a register mentioned in pre_inc, pre_dec, post_inc or
    post_dec is not permitted within the same instruction").  This patch
    fixes PR target/106122 by explicitly checking for SP_REG in the
    problematic peephole2.
    
    2022-07-01  Roger Sayle  <roger@nextmovesoftware.com>
    
    gcc/ChangeLog
            PR target/106122
            * config/i386/i386.md (peephole2): Avoid generating pop %esp
            when optimizing for size.
    
    gcc/testsuite/ChangeLog
            PR target/106122
            * gcc.target/i386/pr106122.c: New test case.

Diff:
---
 gcc/config/i386/i386.md                  |  3 ++-
 gcc/testsuite/gcc.target/i386/pr106122.c | 15 +++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 646a556a811..34018144e5f 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2589,7 +2589,8 @@
   "optimize_insn_for_size_p () && optimize_size > 1
    && operands[1] != const0_rtx
    && IN_RANGE (INTVAL (operands[1]), -128, 127)
-   && !ix86_red_zone_used"
+   && !ix86_red_zone_used
+   && REGNO (operands[0]) != SP_REG"
   [(set (match_dup 2) (match_dup 1))
    (set (match_dup 0) (match_dup 3))]
 {
diff --git a/gcc/testsuite/gcc.target/i386/pr106122.c b/gcc/testsuite/gcc.target/i386/pr106122.c
new file mode 100644
index 00000000000..7d24ed3376d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr106122.c
@@ -0,0 +1,15 @@
+/* PR middle-end/106122 */
+/* { dg-do compile } */
+/* { dg-options "-Oz" } */
+
+register volatile int a __asm__("%esp");
+void foo (void *);
+void bar (void *);
+
+void
+baz (void)
+{
+  foo (__builtin_return_address (0));
+  a = 0;
+  bar (__builtin_return_address (0));
+}