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* [gcc(refs/users/meissner/heads/work093)] Allow KF/TF conversions in IEEE 128-bit insns.
@ 2022-07-07 16:32 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2022-07-07 16:32 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5e30a509703c8ce1eed496010f320a557f6a9340
commit 5e30a509703c8ce1eed496010f320a557f6a9340
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Jul 7 12:31:40 2022 -0400
Allow KF/TF conversions in IEEE 128-bit insns.
2022-07-07 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/predicate.md (kf_or_tf_operand): New predicate.
* config/rs6000/rs6000.md (add<mode>3_odd): Use kf_or_tf_operand
instead of altivec_register_operand.
(sub<mode>3_odd): Likewise.
(mul<mode>3_odd): Likewise.
(div<mode>3_odd): Likewise.
(sqrt<mode>2_odd): Likewise.
(fma<mode>4_odd): Likewise.
(fms<mode>4_odd): Likewise.
(nfma<mode>4_odd): Likewise.
(nfms<mode>4_odd): Likewise.
* config/rs6000/vsx.md (xsxexpqp_<mode>): Likewise.
(xsxsigqp_<mode>): Likewise.
(xsiexpqpf_<mode>): Likewise.
(xscmpexpqp_<code>_<mode>): Likewise.
(xscmpexpqp_<code>_<mode>): Likewise.
(xststdcqp_<mode>): Likewise.
(xststdcnegqp_<mode>): Likewise.
(xststdcqp_<mode>): Likewise.
Diff:
---
gcc/config/rs6000/predicates.md | 26 +++++++++++++++++++++++++
gcc/config/rs6000/rs6000.md | 42 ++++++++++++++++++++---------------------
gcc/config/rs6000/vsx.md | 20 ++++++++++----------
3 files changed, 57 insertions(+), 31 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index b1fcc69bb60..873dbbb22f9 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -2064,3 +2064,29 @@
else
return false;
})
+
+;; Return 1 if the argument is KFmode or TFmode (when TFmode is IEEE 128-bit).
+;; Include various conversions between these formats. This allows passing long
+;; double to IEEE 128-bit built-ins without separate conversions.
+;;
+;; Since all of the instructions that operate on IEEE 128-bit require Altivec
+;; registers, check that the register is an Altivec register.
+(define_predicate "kf_or_tf_operand"
+ (match_code "reg,subreg,float_extend,float_truncate")
+{
+ if (mode == VOIDmode)
+ mode = GET_MODE (op);
+
+ if (!FLOAT128_IEEE_P (mode))
+ return 0;
+
+ if (GET_CODE (op) == FLOAT_EXTEND || GET_CODE (op) == FLOAT_TRUNCATE)
+ {
+ op = XEXP (op, 0);
+ mode = GET_MODE (op);
+ if (!FLOAT128_IEEE_P (mode))
+ return 0;
+ }
+
+ return altivec_register_operand (op, mode);
+})
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ec39358ebe8..e70438b519b 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -15180,8 +15180,8 @@
(define_insn "add<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")
+ (match_operand:IEEE128 2 "kf_or_tf_operand" "v")]
UNSPEC_ADD_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsaddqpo %0,%1,%2"
@@ -15191,8 +15191,8 @@
(define_insn "sub<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")
+ (match_operand:IEEE128 2 "kf_or_tf_operand" "v")]
UNSPEC_SUB_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xssubqpo %0,%1,%2"
@@ -15202,8 +15202,8 @@
(define_insn "mul<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")
+ (match_operand:IEEE128 2 "kf_or_tf_operand" "v")]
UNSPEC_MUL_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmulqpo %0,%1,%2"
@@ -15213,8 +15213,8 @@
(define_insn "div<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")
+ (match_operand:IEEE128 2 "kf_or_tf_operand" "v")]
UNSPEC_DIV_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsdivqpo %0,%1,%2"
@@ -15224,7 +15224,7 @@
(define_insn "sqrt<mode>2_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")]
UNSPEC_SQRT_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xssqrtqpo %0,%1"
@@ -15234,9 +15234,9 @@
(define_insn "fma<mode>4_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")
- (match_operand:IEEE128 3 "altivec_register_operand" "0")]
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")
+ (match_operand:IEEE128 2 "kf_or_tf_operand" "v")
+ (match_operand:IEEE128 3 "kf_or_tf_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmaddqpo %0,%1,%2"
@@ -15246,10 +15246,10 @@
(define_insn "*fms<mode>4_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "%v")
+ (match_operand:IEEE128 2 "kf_or_tf_operand" "v")
(neg:IEEE128
- (match_operand:IEEE128 3 "altivec_register_operand" "0"))]
+ (match_operand:IEEE128 3 "kf_or_tf_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmsubqpo %0,%1,%2"
@@ -15260,9 +15260,9 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(neg:IEEE128
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")
- (match_operand:IEEE128 3 "altivec_register_operand" "0")]
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "%v")
+ (match_operand:IEEE128 2 "kf_or_tf_operand" "v")
+ (match_operand:IEEE128 3 "kf_or_tf_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD)))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmaddqpo %0,%1,%2"
@@ -15273,10 +15273,10 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(neg:IEEE128
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "%v")
+ (match_operand:IEEE128 2 "kf_or_tf_operand" "v")
(neg:IEEE128
- (match_operand:IEEE128 3 "altivec_register_operand" "0"))]
+ (match_operand:IEEE128 3 "kf_or_tf_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD)))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmsubqpo %0,%1,%2"
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e226a93bbe5..87efdaa1756 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5087,7 +5087,7 @@
;; VSX Scalar Extract Exponent Quad-Precision
(define_insn "xsxexpqp_<mode>"
[(set (match_operand:DI 0 "altivec_register_operand" "=v")
- (unspec:DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
+ (unspec:DI [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")]
UNSPEC_VSX_SXEXPDP))]
"TARGET_P9_VECTOR"
"xsxexpqp %0,%1"
@@ -5105,7 +5105,7 @@
;; VSX Scalar Extract Significand Quad-Precision
(define_insn "xsxsigqp_<mode>"
[(set (match_operand:TI 0 "altivec_register_operand" "=v")
- (unspec:TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
+ (unspec:TI [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")]
UNSPEC_VSX_SXSIG))]
"TARGET_P9_VECTOR"
"xsxsigqp %0,%1"
@@ -5124,7 +5124,7 @@
(define_insn "xsiexpqpf_<mode>"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")
(match_operand:DI 2 "altivec_register_operand" "v")]
UNSPEC_VSX_SIEXPQP))]
"TARGET_P9_VECTOR"
@@ -5200,8 +5200,8 @@
[(set (match_dup 3)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "vsx_register_operand" "v")
- (match_operand:IEEE128 2 "vsx_register_operand" "v")]
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")
+ (match_operand:IEEE128 2 "kf_or_tf_operand" "v")]
UNSPEC_VSX_SCMPEXPQP)
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
@@ -5221,8 +5221,8 @@
(define_insn "*xscmpexpqp"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP
- (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+ (unspec:IEEE128 [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")
+ (match_operand:IEEE128 2 "kf_or_tf_operand" "v")]
UNSPEC_VSX_SCMPEXPQP)
(match_operand:SI 3 "zero_constant" "j")))]
"TARGET_P9_VECTOR"
@@ -5238,7 +5238,7 @@
[(set (match_dup 3)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")
(match_operand:SI 2 "u7bit_cint_operand" "n")]
UNSPEC_VSX_STSTDC)
(const_int 0)))
@@ -5276,7 +5276,7 @@
[(set (match_dup 2)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")
(const_int 0)]
UNSPEC_VSX_STSTDC)
(const_int 0)))
@@ -5310,7 +5310,7 @@
[(set (match_operand:CCFP 0 "" "=y")
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ [(match_operand:IEEE128 1 "kf_or_tf_operand" "v")
(match_operand:SI 2 "u7bit_cint_operand" "n")]
UNSPEC_VSX_STSTDC)
(const_int 0)))]
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work093)] Allow KF/TF conversions in IEEE 128-bit insns.
@ 2022-07-07 20:21 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2022-07-07 20:21 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1d832dc83b09e386be03bb6455687d7e939c991c
commit 1d832dc83b09e386be03bb6455687d7e939c991c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Jul 7 16:21:19 2022 -0400
Allow KF/TF conversions in IEEE 128-bit insns.
2022-07-07 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-c.cc (is_float128_p): Update comment.
(rs6000_builtin_type_compatible): Do not consider _Float128 to be
compatible with long double under -mabi=ieeelongdouble.
Diff:
---
gcc/config/rs6000/rs6000-c.cc | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index b9d3aa06e40..5808ab046e0 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -812,8 +812,11 @@ rs6000_builtin_type (int id)
/* Check whether the type of an argument, T, is compatible with a type ID
stored into a struct altivec_builtin_types. Integer types are considered
compatible; otherwise, the language hook lang_hooks.types_compatible_p makes
- the decision. Also allow long double and _Float128 to be compatible if
- -mabi=ieeelongdouble. */
+ the decision.
+
+ In the past, we used to consider _Float128 and long double to be compatible
+ under -mabi=ieeelongdouble. We no longer consider them compatible and use
+ the overload mechanism to deal with KFmode vs. TFmode types. */
static inline bool
is_float128_p (tree t)
@@ -836,7 +839,8 @@ rs6000_builtin_type_compatible (tree parmtype, tree argtype)
return true;
if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
- && is_float128_p (parmtype) && is_float128_p (argtype))
+ && is_float128_p (parmtype) && is_float128_p (argtype)
+ && TYPE_MODE (parmtype) == TYPE_MODE (argtype))
return true;
if (POINTER_TYPE_P (parmtype) && POINTER_TYPE_P (argtype))
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