[gcc(refs/users/meissner/heads/work095)] Remove setting -mblock-ops-vector-pair on power10.

[gcc(refs/users/meissner/heads/work095)] Remove setting -mblock-ops-vector-pair on power10.

[Michael Meissner]

https://gcc.gnu.org/g:e5a8dfceb96a3ef5bde9ff7cd352cdf5902b9d32

commit e5a8dfceb96a3ef5bde9ff7cd352cdf5902b9d32
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon Jul 18 15:39:26 2022 -0400

    Remove setting -mblock-ops-vector-pair on power10.
    
    Testing has shown that using the load vector pair and store vector pair
    instructions for block moves has some performance issues on power10.  This
    patch does not set this option by default.  If it is a win in other
    machines, this flag can be set in the ISA options.
    
    2022-07-18   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.cc (rs6000_option_override_internal):
            Remove code setting -mblock-ops-vector-pair by default on
            power10.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 3ff16b8ae04..667f83b1dfd 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4139,17 +4139,6 @@ rs6000_option_override_internal (bool global_init_p)
 	rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX;
     }
 
-  if (!(rs6000_isa_flags_explicit & OPTION_MASK_BLOCK_OPS_VECTOR_PAIR))
-    {
-      /* Do not generate lxvp and stxvp on power10 since there are some
-	 performance issues.  */
-      if (TARGET_MMA && TARGET_EFFICIENT_UNALIGNED_VSX
-	  && rs6000_tune != PROCESSOR_POWER10)
-	rs6000_isa_flags |= OPTION_MASK_BLOCK_OPS_VECTOR_PAIR;
-      else
-	rs6000_isa_flags &= ~OPTION_MASK_BLOCK_OPS_VECTOR_PAIR;
-    }
-
   /* Use long double size to select the appropriate long double.  We use
      TYPE_PRECISION to differentiate the 3 different long double types.  We map
      128 into the precision used for TFmode.  */