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* [gcc(refs/users/meissner/heads/work095)] Make BLOCK_OPTS options settable with ISA flags.
@ 2022-07-19 21:20 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2022-07-19 21:20 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:df4dc6a3e8764ce905c7e51497e6bca4413ce793
commit df4dc6a3e8764ce905c7e51497e6bca4413ce793
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jul 19 17:20:16 2022 -0400
Make BLOCK_OPTS options settable with ISA flags.
In wanting to turn off block moves from generating load and store vector
pair operations on the power10, I noticed that the options for controlling
the code block moves generate (OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX and
OPTION_MASK_BLOCK_OPS_VECTOR_PAIR) were not set in POWERPC_MASKS. It is
possible in future CPUs we might want to enable these options
automatically. This code moves these options to POWERPC_MASKS.
2022-07-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add
OPTION_MASK_BLOCK_OPS_VECTOR_PAIR and
OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 2 --
1 file changed, 2 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index f3d2692cb86..c3825bcccd8 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -122,8 +122,6 @@
/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
- | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
- | OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX \
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
^ permalink raw reply [flat|nested] 2+ messages in thread
* [gcc(refs/users/meissner/heads/work095)] Make BLOCK_OPTS options settable with ISA flags.
@ 2022-07-18 19:32 Michael Meissner
0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2022-07-18 19:32 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2ea1fb851857d8031d5cdc8f60cb9dfb9d473d47
commit 2ea1fb851857d8031d5cdc8f60cb9dfb9d473d47
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Jul 18 15:31:46 2022 -0400
Make BLOCK_OPTS options settable with ISA flags.
In wanting to turn off block moves from generating load and store vector
pair operations on the power10, I noticed that the options for controlling
the code block moves generate (OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX and
OPTION_MASK_BLOCK_OPS_VECTOR_PAIR) were not set in POWERPC_MASKS. It is
possible in future CPUs we might want to enable these options
automatically. This code moves these options to POWERPC_MASKS.
2022-07-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add
OPTION_MASK_BLOCK_OPS_VECTOR_PAIR and
OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index c3825bcccd8..f3d2692cb86 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -122,6 +122,8 @@
/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
+ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
+ | OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX \
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
^ permalink raw reply [flat|nested] 2+ messages in thread
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