[gcc r13-1894] amdgcn: 64-bit not

[gcc r13-1894] amdgcn: 64-bit not

[Andrew Stubbs]

https://gcc.gnu.org/g:8f4d9c1dedac54942ad28cc1647d48959bec9e77

commit r13-1894-g8f4d9c1dedac54942ad28cc1647d48959bec9e77
Author: Andrew Stubbs <ams@codesourcery.com>
Date:   Fri Jul 15 15:28:44 2022 +0100

    amdgcn: 64-bit not
    
    This makes the auto-vectorizer happier when handling masks.
    
    gcc/ChangeLog:
    
            * config/gcn/gcn.md (one_cmpldi2): New.

Diff:
---
 gcc/config/gcn/gcn.md | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index 033c1708e88..70a769babc4 100644
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -1676,6 +1676,26 @@
 ;; }}}
 ;; {{{ ALU: generic 64-bit
 
+(define_insn_and_split "one_cmpldi2"
+  [(set (match_operand:DI 0 "register_operand"        "=Sg,    v")
+	(not:DI (match_operand:DI 1 "gcn_alu_operand" "SgA,vSvDB")))
+   (clobber (match_scratch:BI 2			      "=cs,    X"))]
+  ""
+  "#"
+  "reload_completed"
+  [(parallel [(set (match_dup 3) (not:SI (match_dup 4)))
+	      (clobber (match_dup 2))])
+   (parallel [(set (match_dup 5) (not:SI (match_dup 6)))
+	      (clobber (match_dup 2))])]
+  {
+    operands[3] = gcn_operand_part (DImode, operands[0], 0);
+    operands[4] = gcn_operand_part (DImode, operands[1], 0);
+    operands[5] = gcn_operand_part (DImode, operands[0], 1);
+    operands[6] = gcn_operand_part (DImode, operands[1], 1);
+  }
+  [(set_attr "type" "mult")]
+)
+
 (define_code_iterator vec_and_scalar64_com [and ior xor])
 
 (define_insn_and_split "<expander>di3"