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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work097)] Revert patch.
Date: Wed, 10 Aug 2022 18:45:09 +0000 (GMT) [thread overview]
Message-ID: <20220810184509.E69253858430@sourceware.org> (raw)
https://gcc.gnu.org/g:bfe95056d95934d6e330ae9a75f2746082a6d72d
commit bfe95056d95934d6e330ae9a75f2746082a6d72d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Aug 10 14:44:34 2022 -0400
Revert patch.
2022-08-10 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
* config/rs6000/predicates.md (ieee128_operand): New predicate.
(ibm128_operand): Likewise.
* config/rs6000/rs6000.md (unpack<mode>): Use ibm128_operand instead of
register_operand.
(unpack<mode>_dm): Likewise.
(unpack<mode>_nodm): Likewise.
(pack<mode>_hard): Likewise.
(unpack<mode>): Likewise.
(trunc<mode>sf2_hw): Use ieee128_operand instead of
altivec_register_operand.
(add<mode>3_odd): Likewise.
(sub<mode>3_odd): Likewise.
(mul<mode>3_odd): Likewise.
(div<mode>3_odd): Likewise.
(sqrt<mode>2_odd): Likewise.
(fma<mode>4_odd): Likewise.
(fms<mode>4_odd): Likewise.
(nfma<mode>4_odd): Likewise.
(nfms<mode>4_odd): Likewise.
(trunc<mode>df2_odd): Likewise.
* config/rs6000/vsx.md (xsxexpqp_<mode>): Use ieee128_operand instead of
altivec_register_operand.
(xsxsigqp_<mode>): Likewise.
(xsiexpqpf_<mode>): Likewise.
(xsiexpqp_<mode>): Likewise.
(xscmpexpqp_<code>_<mode>): Likewise.
(xscmpexpqp_<code>_<mode>): Likewise.
(xststdcqp_<mode>): Likewise.
(xststdcnegqp_<mode>): Likewise.
(xststdcqp_<mode): Likewise.
Diff:
---
gcc/config/rs6000/predicates.md | 37 -------------------
gcc/config/rs6000/rs6000.md | 80 ++++++++++++++++++++---------------------
gcc/config/rs6000/vsx.md | 24 ++++++-------
3 files changed, 52 insertions(+), 89 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 2839ca73d95..b1fcc69bb60 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -119,43 +119,6 @@
return VSX_REGNO_P (REGNO (op));
})
-;; Return 1 if op is an IEEE 128-bit floating point type that is in a
-;; traditional Altivec register in order to do one of the IEEE 128-bit hardware
-;; instructions. We allow the operand mode to be different from the mode in
-;; the call to allow using either KFmode or TFmode, assuming the mode supports
-;; IEEE 128-bits. This way combinations of long double and __float128 will
-;; work when long double uses the IEEE 128-bit format without having to have
-;; insns that recognize the pattern with convert insns used.
-(define_predicate "ieee128_operand"
- (match_code "reg,subreg")
-{
- if (GET_MODE (op) != VOIDmode)
- mode = GET_MODE (op);
-
- if (!FLOAT128_IEEE_P (mode))
- return 0;
-
- return altivec_register_operand (op, mode);
-})
-
-;; Return 1 if op is an IBM 128-bit floating point type. We allow the operand
-;; mode to be different from the mode in the call to allow using either IFmode
-;; or TFmode, assuming the mode supports IBM 128-bits. This way combinations
-;; of long double and __ibm128 will work when long double uses the IBM 128-bit
-;; format without having to have insns that recognize the pattern with convert
-;; insns used.
-(define_predicate "ibm128_operand"
- (match_code "reg,subreg")
-{
- if (GET_MODE (op) != VOIDmode)
- mode = GET_MODE (op);
-
- if (!FLOAT128_IBM_P (mode))
- return 0;
-
- return register_operand (op, mode);
-})
-
;; Return 1 if op is a vector register that operates on floating point vectors
;; (either altivec or VSX).
(define_predicate "vfloat_operand"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4a2dc089151..e17252bb8de 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -14614,7 +14614,7 @@
(define_expand "unpack<mode>"
[(set (match_operand:<FP128_64> 0 "nonimmediate_operand")
(unspec:<FP128_64>
- [(match_operand:FMOVE128 1 "ibm128_operand")
+ [(match_operand:FMOVE128 1 "register_operand")
(match_operand:QI 2 "const_0_to_1_operand")]
UNSPEC_UNPACK_128BIT))]
"FLOAT128_2REG_P (<MODE>mode)"
@@ -14623,7 +14623,7 @@
(define_insn_and_split "unpack<mode>_dm"
[(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
(unspec:<FP128_64>
- [(match_operand:FMOVE128 1 "ibm128_operand" "d,d,r,d,r")
+ [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
(match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
UNSPEC_UNPACK_128BIT))]
"TARGET_POWERPC64 && TARGET_DIRECT_MOVE && FLOAT128_2REG_P (<MODE>mode)"
@@ -14646,7 +14646,7 @@
(define_insn_and_split "unpack<mode>_nodm"
[(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,m")
(unspec:<FP128_64>
- [(match_operand:FMOVE128 1 "ibm128_operand" "d,d,r")
+ [(match_operand:FMOVE128 1 "register_operand" "d,d,r")
(match_operand:QI 2 "const_0_to_1_operand" "i,i,i")]
UNSPEC_UNPACK_128BIT))]
"(!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE) && FLOAT128_2REG_P (<MODE>mode)"
@@ -14680,7 +14680,7 @@
})
(define_insn_and_split "pack<mode>_hard"
- [(set (match_operand:FMOVE128 0 "ibm128_operand" "=&d")
+ [(set (match_operand:FMOVE128 0 "register_operand" "=&d")
(unspec:FMOVE128
[(match_operand:<FP128_64> 1 "register_operand" "d")
(match_operand:<FP128_64> 2 "register_operand" "d")]
@@ -14733,7 +14733,7 @@
(define_insn "unpack<mode>"
[(set (match_operand:DI 0 "register_operand" "=wa,wa")
- (unspec:DI [(match_operand:FMOVE128_VSX 1 "ibm128_operand" "0,wa")
+ (unspec:DI [(match_operand:FMOVE128_VSX 1 "register_operand" "0,wa")
(match_operand:QI 2 "const_0_to_1_operand" "O,i")]
UNSPEC_UNPACK_128BIT))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
@@ -14747,7 +14747,7 @@
[(set_attr "type" "vecperm")])
(define_insn "pack<mode>"
- [(set (match_operand:FMOVE128_VSX 0 "ibm128_operand" "=wa")
+ [(set (match_operand:FMOVE128_VSX 0 "register_operand" "=wa")
(unspec:FMOVE128_VSX
[(match_operand:DI 1 "register_operand" "wa")
(match_operand:DI 2 "register_operand" "wa")]
@@ -14984,7 +14984,7 @@
(define_insn_and_split "trunc<mode>sf2_hw"
[(set (match_operand:SF 0 "vsx_register_operand" "=wa")
(float_truncate:SF
- (match_operand:IEEE128 1 "ieee128_operand" "v")))
+ (match_operand:IEEE128 1 "altivec_register_operand" "v")))
(clobber (match_scratch:DF 2 "=v"))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"#"
@@ -15213,10 +15213,10 @@
;; IEEE 128-bit instructions with round to odd semantics
(define_insn "add<mode>3_odd"
- [(set (match_operand:IEEE128 0 "ieee128_operand" "=v")
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_ADD_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsaddqpo %0,%1,%2"
@@ -15224,10 +15224,10 @@
(set_attr "size" "128")])
(define_insn "sub<mode>3_odd"
- [(set (match_operand:IEEE128 0 "ieee128_operand" "=v")
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_SUB_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xssubqpo %0,%1,%2"
@@ -15235,10 +15235,10 @@
(set_attr "size" "128")])
(define_insn "mul<mode>3_odd"
- [(set (match_operand:IEEE128 0 "ieee128_operand" "=v")
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_MUL_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmulqpo %0,%1,%2"
@@ -15246,10 +15246,10 @@
(set_attr "size" "128")])
(define_insn "div<mode>3_odd"
- [(set (match_operand:IEEE128 0 "ieee128_operand" "=v")
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_DIV_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsdivqpo %0,%1,%2"
@@ -15257,9 +15257,9 @@
(set_attr "size" "128")])
(define_insn "sqrt<mode>2_odd"
- [(set (match_operand:IEEE128 0 "ieee128_operand" "=v")
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_SQRT_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xssqrtqpo %0,%1"
@@ -15267,11 +15267,11 @@
(set_attr "size" "128")])
(define_insn "fma<mode>4_odd"
- [(set (match_operand:IEEE128 0 "ieee128_operand" "=v")
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")
- (match_operand:IEEE128 3 "ieee128_operand" "0")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")
+ (match_operand:IEEE128 3 "altivec_register_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmaddqpo %0,%1,%2"
@@ -15279,12 +15279,12 @@
(set_attr "size" "128")])
(define_insn "*fms<mode>4_odd"
- [(set (match_operand:IEEE128 0 "ieee128_operand" "=v")
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "%v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")
(neg:IEEE128
- (match_operand:IEEE128 3 "ieee128_operand" "0"))]
+ (match_operand:IEEE128 3 "altivec_register_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmsubqpo %0,%1,%2"
@@ -15292,12 +15292,12 @@
(set_attr "size" "128")])
(define_insn "*nfma<mode>4_odd"
- [(set (match_operand:IEEE128 0 "ieee128_operand" "=v")
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(neg:IEEE128
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "%v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")
- (match_operand:IEEE128 3 "ieee128_operand" "0")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")
+ (match_operand:IEEE128 3 "altivec_register_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD)))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmaddqpo %0,%1,%2"
@@ -15305,13 +15305,13 @@
(set_attr "size" "128")])
(define_insn "*nfms<mode>4_odd"
- [(set (match_operand:IEEE128 0 "ieee128_operand" "=v")
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(neg:IEEE128
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "%v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")
(neg:IEEE128
- (match_operand:IEEE128 3 "ieee128_operand" "0"))]
+ (match_operand:IEEE128 3 "altivec_register_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD)))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmsubqpo %0,%1,%2"
@@ -15320,7 +15320,7 @@
(define_insn "trunc<mode>df2_odd"
[(set (match_operand:DF 0 "vsx_register_operand" "=v")
- (unspec:DF [(match_operand:IEEE128 1 "ieee128_operand" "v")]
+ (unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_TRUNC_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscvqpdpo %0,%1"
@@ -15330,8 +15330,8 @@
;; IEEE 128-bit comparisons
(define_insn "*cmp<mode>_hw"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (compare:CCFP (match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")))]
+ (compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscmpuqp %0,%1,%2"
[(set_attr "type" "veccmp")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c6b6b67d612..e226a93bbe5 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5087,7 +5087,7 @@
;; VSX Scalar Extract Exponent Quad-Precision
(define_insn "xsxexpqp_<mode>"
[(set (match_operand:DI 0 "altivec_register_operand" "=v")
- (unspec:DI [(match_operand:IEEE128 1 "ieee128_operand" "v")]
+ (unspec:DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_VSX_SXEXPDP))]
"TARGET_P9_VECTOR"
"xsxexpqp %0,%1"
@@ -5105,7 +5105,7 @@
;; VSX Scalar Extract Significand Quad-Precision
(define_insn "xsxsigqp_<mode>"
[(set (match_operand:TI 0 "altivec_register_operand" "=v")
- (unspec:TI [(match_operand:IEEE128 1 "ieee128_operand" "v")]
+ (unspec:TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_VSX_SXSIG))]
"TARGET_P9_VECTOR"
"xsxsigqp %0,%1"
@@ -5122,9 +5122,9 @@
;; VSX Scalar Insert Exponent Quad-Precision Floating Point Argument
(define_insn "xsiexpqpf_<mode>"
- [(set (match_operand:IEEE128 0 "ieee128_operand" "=v")
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:DI 2 "altivec_register_operand" "v")]
UNSPEC_VSX_SIEXPQP))]
"TARGET_P9_VECTOR"
@@ -5133,7 +5133,7 @@
;; VSX Scalar Insert Exponent Quad-Precision
(define_insn "xsiexpqp_<mode>"
- [(set (match_operand:IEEE128 0 "ieee128_operand" "=v")
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128 [(match_operand:TI 1 "altivec_register_operand" "v")
(match_operand:DI 2 "altivec_register_operand" "v")]
UNSPEC_VSX_SIEXPQP))]
@@ -5200,8 +5200,8 @@
[(set (match_dup 3)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "vsx_register_operand" "v")
+ (match_operand:IEEE128 2 "vsx_register_operand" "v")]
UNSPEC_VSX_SCMPEXPQP)
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
@@ -5221,8 +5221,8 @@
(define_insn "*xscmpexpqp"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP
- (unspec:IEEE128 [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_VSX_SCMPEXPQP)
(match_operand:SI 3 "zero_constant" "j")))]
"TARGET_P9_VECTOR"
@@ -5238,7 +5238,7 @@
[(set (match_dup 3)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:SI 2 "u7bit_cint_operand" "n")]
UNSPEC_VSX_STSTDC)
(const_int 0)))
@@ -5276,7 +5276,7 @@
[(set (match_dup 2)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
(const_int 0)]
UNSPEC_VSX_STSTDC)
(const_int 0)))
@@ -5310,7 +5310,7 @@
[(set (match_operand:CCFP 0 "" "=y")
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:SI 2 "u7bit_cint_operand" "n")]
UNSPEC_VSX_STSTDC)
(const_int 0)))]
next reply other threads:[~2022-08-10 18:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-10 18:45 Michael Meissner [this message]
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