[gcc(refs/users/pinskia/heads/riscvbit)] [RISC-V] Fix 32bit riscv with zbs extension enabled

[gcc(refs/users/pinskia/heads/riscvbit)] [RISC-V] Fix 32bit riscv with zbs extension enabled

[Andrew Pinski]

https://gcc.gnu.org/g:1e248ea28faa931b7af63246ff0af98d8006adb0

commit 1e248ea28faa931b7af63246ff0af98d8006adb0
Author: Andrew Pinski <apinski@marvell.com>
Date:   Thu Aug 4 19:48:17 2022 -0700

    [RISC-V] Fix 32bit riscv with zbs extension enabled
    
    The problem here was a disconnect between splittable_const_int_operand
    predicate and the function riscv_build_integer_1 for 32bits with zbs enabled.
    The splittable_const_int_operand predicate had a check for TARGET_64BIT which
    was not needed so this patch removed it.
    
    Committed as obvious after a build for risc32-elf configured with --with-arch=rv32imac_zba_zbb_zbc_zbs.
    
    Thanks,
    Andrew Pinski
    
    gcc/ChangeLog:
    
            * config/riscv/predicates.md (splittable_const_int_operand):
            Remove the check for TARGET_64BIT for single bit const values.
    
    Signed-off-by: Andrew Pinski <apinski@marvell.com>
    Change-Id: Id542ec511851993333a88fac54f78a04dcf2ca3a

Diff:
---
 gcc/config/riscv/predicates.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 90db5dfcdd5..e98db2cb574 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -76,7 +76,7 @@
 
   /* Check whether the constant can be loaded in a single
      instruction with zbs extensions.  */
-  if (TARGET_64BIT && TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (INTVAL (op)))
+  if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (INTVAL (op)))
     return false;
 
   /* Otherwise check whether the constant can be loaded in a single