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* [gcc(refs/users/pinskia/heads/riscvbit)] [RISCV] Use a constraint for bset<mode>_1_mask
@ 2022-08-15 23:14 Andrew Pinski
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From: Andrew Pinski @ 2022-08-15 23:14 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:26537f58e6664ee27607ecf706c2e8c3c1c31f0f
commit 26537f58e6664ee27607ecf706c2e8c3c1c31f0f
Author: Andrew Pinski <apinski@marvell.com>
Date: Mon Aug 15 18:39:17 2022 +0000
[RISCV] Use a constraint for bset<mode>_1_mask
Even though there might not be a pass (right now) that
changes the constants post register allocation, it
is better if we add the constraint to future prove
the patterns here.
gcc/ChangeLog:
* config/riscv/bitmanip.md:
* config/riscv/constraints.md (DsS):
(DsD):
* config/riscv/iterators.md (DsD):
Change-Id: I2dfed93376498b0dbed6c317972893b75cf65ac2
Diff:
---
gcc/config/riscv/bitmanip.md | 4 ++--
gcc/config/riscv/constraints.md | 12 ++++++++++++
gcc/config/riscv/iterators.md | 1 +
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 73a36f7751b..d362f526e79 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -273,7 +273,7 @@
(ior:X (ashift:X (const_int 1)
(subreg:QI
(and:X (match_operand:X 2 "register_operand" "r")
- (match_operand 3 "<X:shiftm1>" "i")) 0))
+ (match_operand 3 "<X:shiftm1>" "<X:shiftm1p>")) 0))
(match_operand:X 1 "register_operand" "r")))]
"TARGET_ZBS"
"bset\t%0,%1,%2"
@@ -292,7 +292,7 @@
(ashift:X (const_int 1)
(subreg:QI
(and:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "<X:shiftm1>" "i")) 0)))]
+ (match_operand 2 "<X:shiftm1>" "<X:shiftm1p>")) 0)))]
"TARGET_ZBS"
"bset\t%0,x0,%1"
[(set_attr "type" "bitmanip")])
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 61b84875fd9..444870ad060 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -60,6 +60,18 @@
(and (match_code "const_int")
(match_test "IN_RANGE (ival, 1, 3)")))
+(define_constraint "DsS"
+ "@internal
+ 31 immediate"
+ (and (match_code "const_int")
+ (match_test "ival == 31")))
+
+(define_constraint "DsD"
+ "@internal
+ 63 immediate"
+ (and (match_code "const_int")
+ (match_test "ival == 63")))
+
;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
;; not available in RV32.
(define_constraint "G"
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 7edc4e05fdd..f06d60d2366 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -114,6 +114,7 @@
; bitmanip mode attribute
(define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
+(define_mode_attr shiftm1p [(SI "DsS") (DI "DsD")])
;; -------------------------------------------------------------------
;; Code Iterators
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