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* [gcc r13-2329] RISC-V: Add csrr vlenb instruction.
@ 2022-09-01 2:04 Kito Cheng
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From: Kito Cheng @ 2022-09-01 2:04 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8fe75147a948ceab6fb9afbe0ee698517ce1dda0
commit r13-2329-g8fe75147a948ceab6fb9afbe0ee698517ce1dda0
Author: zhongjuzhe <juzhe.zhong@rivai.ai>
Date: Tue Aug 30 14:20:27 2022 +0800
RISC-V: Add csrr vlenb instruction.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Add cost of poly_int.
(riscv_output_move): Add csrr vlenb assembly.
* config/riscv/riscv.md (move_type): Add csrr vlenb type.
(ext): New attribute.
(ext_enabled): Ditto.
(enabled): Ditto.
Diff:
---
gcc/config/riscv/riscv.cc | 12 +++++++
gcc/config/riscv/riscv.md | 79 ++++++++++++++++++++++++++++++++++-------------
2 files changed, 69 insertions(+), 22 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5e68fccbb9e..30cbf00542e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1136,6 +1136,12 @@ riscv_const_insns (rtx x)
case LABEL_REF:
return riscv_symbol_insns (riscv_classify_symbol (x));
+ /* TODO: In RVV, we get CONST_POLY_INT by using csrr VLENB
+ instruction and several scalar shift or mult instructions,
+ it is so far unknown. We set it to 4 temporarily. */
+ case CONST_POLY_INT:
+ return 4;
+
default:
return 0;
}
@@ -2507,6 +2513,12 @@ riscv_output_move (rtx dest, rtx src)
return "fld\t%0,%1";
}
}
+ if (dest_code == REG && GP_REG_P (REGNO (dest)) && src_code == CONST_POLY_INT)
+ {
+ /* We only want a single full vector register VLEN read after reload. */
+ gcc_assert (known_eq (rtx_to_poly_int64 (src), BYTES_PER_RISCV_VECTOR));
+ return "csrr\t%0,vlenb";
+ }
gcc_unreachable ();
}
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 63bb3c8debc..2bfab198370 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -148,7 +148,7 @@
;; scheduling type to be "multi" instead.
(define_attr "move_type"
"unknown,load,fpload,store,fpstore,mtc,mfc,move,fmove,
- const,logical,arith,andi,shift_shift"
+ const,logical,arith,andi,shift_shift,rdvlenb"
(const_string "unknown"))
;; Main data type used by the insn
@@ -166,6 +166,35 @@
(const_string "yes")]
(const_string "no")))
+;; ISA attributes.
+(define_attr "ext" "base,f,d,vector"
+ (const_string "base"))
+
+;; True if the extension is enabled.
+(define_attr "ext_enabled" "no,yes"
+ (cond [(eq_attr "ext" "base")
+ (const_string "yes")
+
+ (and (eq_attr "ext" "f")
+ (match_test "TARGET_HARD_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "d")
+ (match_test "TARGET_DOUBLE_FLOAT"))
+ (const_string "yes")
+
+ (and (eq_attr "ext" "vector")
+ (match_test "TARGET_VECTOR"))
+ (const_string "yes")
+ ]
+ (const_string "no")))
+
+;; Attribute to control enable or disable instructions.
+(define_attr "enabled" "no,yes"
+ (cond [(eq_attr "ext_enabled" "no")
+ (const_string "no")]
+ (const_string "yes")))
+
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
@@ -326,7 +355,8 @@
(eq_attr "dword_mode" "yes"))
(const_string "multi")
(eq_attr "move_type" "move") (const_string "move")
- (eq_attr "move_type" "const") (const_string "const")]
+ (eq_attr "move_type" "const") (const_string "const")
+ (eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
(const_string "unknown")))
;; Length of instruction in bytes.
@@ -1633,24 +1663,26 @@
})
(define_insn "*movdi_32bit"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m, *f,*f,*r,*f,*m")
- (match_operand:DI 1 "move_operand" " r,i,m,r,*J*r,*m,*f,*f,*f"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m, *f,*f,*r,*f,*m,r")
+ (match_operand:DI 1 "move_operand" " r,i,m,r,*J*r,*m,*f,*f,*f,vp"))]
"!TARGET_64BIT
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return riscv_output_move (operands[0], operands[1]); }
- [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore")
- (set_attr "mode" "DI")])
+ [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb")
+ (set_attr "mode" "DI")
+ (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")])
(define_insn "*movdi_64bit"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*f,*m")
- (match_operand:DI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,*f"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*f,*m,r")
+ (match_operand:DI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,*f,vp"))]
"TARGET_64BIT
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return riscv_output_move (operands[0], operands[1]); }
- [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore")
- (set_attr "mode" "DI")])
+ [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb")
+ (set_attr "mode" "DI")
+ (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")])
;; 32-bit Integer moves
@@ -1664,13 +1696,14 @@
})
(define_insn "*movsi_internal"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*m")
- (match_operand:SI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*m,r")
+ (match_operand:SI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,vp"))]
"(register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
{ return riscv_output_move (operands[0], operands[1]); }
- [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore")
- (set_attr "mode" "SI")])
+ [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb")
+ (set_attr "mode" "SI")
+ (set_attr "ext" "base,base,base,base,f,f,f,f,vector")])
;; 16-bit Integer moves
@@ -1689,13 +1722,14 @@
})
(define_insn "*movhi_internal"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r")
- (match_operand:HI 1 "move_operand" " r,T,m,rJ,*r*J,*f"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r,r")
+ (match_operand:HI 1 "move_operand" " r,T,m,rJ,*r*J,*f,vp"))]
"(register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode))"
{ return riscv_output_move (operands[0], operands[1]); }
- [(set_attr "move_type" "move,const,load,store,mtc,mfc")
- (set_attr "mode" "HI")])
+ [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb")
+ (set_attr "mode" "HI")
+ (set_attr "ext" "base,base,base,base,f,f,vector")])
;; HImode constant generation; see riscv_move_integer for details.
;; si+si->hi without truncation is legal because of
@@ -1731,13 +1765,14 @@
})
(define_insn "*movqi_internal"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r")
- (match_operand:QI 1 "move_operand" " r,I,m,rJ,*r*J,*f"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r,r")
+ (match_operand:QI 1 "move_operand" " r,I,m,rJ,*r*J,*f,vp"))]
"(register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode))"
{ return riscv_output_move (operands[0], operands[1]); }
- [(set_attr "move_type" "move,const,load,store,mtc,mfc")
- (set_attr "mode" "QI")])
+ [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb")
+ (set_attr "mode" "QI")
+ (set_attr "ext" "base,base,base,base,f,f,vector")])
;; 32-bit floating point moves
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