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* [gcc r13-2330] RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE
@ 2022-09-01 2:04 Kito Cheng
0 siblings, 0 replies; only message in thread
From: Kito Cheng @ 2022-09-01 2:04 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e8c83ab9d5142a305bbd75c7ff0e41eae38433df
commit r13-2330-ge8c83ab9d5142a305bbd75c7ff0e41eae38433df
Author: zhongjuzhe <juzhe.zhong@rivai.ai>
Date: Tue Aug 30 14:27:52 2022 +0800
RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_conditional_register_usage): Add vector
registers.
Diff:
---
gcc/config/riscv/riscv.cc | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 30cbf00542e..675d92c0961 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5438,6 +5438,15 @@ riscv_conditional_register_usage (void)
for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
call_used_regs[regno] = 1;
}
+
+ if (!TARGET_VECTOR)
+ {
+ for (int regno = V_REG_FIRST; regno <= V_REG_LAST; regno++)
+ fixed_regs[regno] = call_used_regs[regno] = 1;
+
+ fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1;
+ fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1;
+ }
}
/* Return a register priority for hard reg REGNO. */
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